On 21 October 2015 at 14:01, Shlomo Pongratz <shlomopongr...@gmail.com> wrote: > On Wednesday, October 21, 2015, Peter Maydell <peter.mayd...@linaro.org> > wrote: >> The system register implementation belongs in the gic code, not >> target-arm/. We already have support for devices that say >> "I have some system registers, please add them to this CPU". >> > > I don't understand. > The system registers are defined in ARM Architecture reference Manual. > It is true that the real implementation is in arm_gicv3_interrupts.c > But the crn, crm, op0, and op1 of the instructions are in CPU domain.
Well, this comes down to "do you want to design the GICv3 emulation to preserve the split the hardware has between the cpu interface and the GIC proper". In hardware there's actually a defined protocol between the two, so you can have CPUs from one implementor that talk to a GIC from another implementor. For QEMU that seems like overkill, as we will only ever have one GICv3 implementation and one CPU implementation. So we should just have the GICv3 provide the CPU system register implementations. But the code for those belongs in hw/intc/: that should call the function for "add these system registers" which we have already: define_arm_cp_regs_with_opaque(). (We use this in hw/arm/pxa2xx_pic, for instance.) thanks -- PMM
