>From 14fe2a651b3f5729f1d402dfcd6eb5f7da0f42b1 Mon Sep 17 00:00:00 2001 From: Chen Gang <gang.chen.5...@gmail.com> Date: Tue, 20 Oct 2015 23:19:02 +0800 Subject: [PATCH] target-tilegx: Implement prefetch instructions in pipe y2
Originally, tilegx qemu only implement prefetch instructions in pipe x1, did not implement them in pipe y2. Signed-off-by: Chen Gang <gang.chen.5...@gmail.com> --- target-tilegx/translate.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 34d45f8..b8ca401 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -2105,6 +2105,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle) unsigned srcbdest = get_SrcBDest_Y2(bundle); const char *mnemonic; TCGMemOp memop; + bool prefetch_nofault = false; switch (OEY2(opc, mode)) { case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2): @@ -2114,6 +2115,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle) case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2): memop = MO_UB; mnemonic = "ld1u"; + prefetch_nofault = (srcbdest == TILEGX_R_ZERO); goto do_load; case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2): memop = MO_TESW; @@ -2122,6 +2124,7 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle) case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2): memop = MO_TEUW; mnemonic = "ld2u"; + prefetch_nofault = (srcbdest == TILEGX_R_ZERO); goto do_load; case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2): memop = MO_TESL; @@ -2130,13 +2133,16 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle) case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2): memop = MO_TEUL; mnemonic = "ld4u"; + prefetch_nofault = (srcbdest == TILEGX_R_ZERO); goto do_load; case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2): memop = MO_TEQ; mnemonic = "ld"; do_load: - tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca), - dc->mmuidx, memop); + if (!prefetch_nofault) { + tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca), + dc->mmuidx, memop); + } qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic, reg_names[srcbdest], reg_names[srca]); return TILEGX_EXCP_NONE; -- 1.9.3
0001-target-tilegx-Implement-prefetch-instructions-in-pip.patch
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