On 16 October 2015 at 18:21, Ilya Lipnitskiy <ilya.lipnits...@gmail.com> wrote: > Hi All, > > I am running into a curious issue with QEMU ARM, maybe a Linux/QEMU > ARM expert could help before I filed a bug report. Is this a QEMU > problem or is there a fundamental problem with my kernel change? QEMU > builds before SHA 6ec1588e handle this kernel change just fine... > > I'm seeing a very early CPU abort if I add L1 cache invalidation logic > in early Linux decompress code in arch/arm/boot/compressed/head.S. > Essentially, if I add a copy of v7_invalidate_l1 from > arch/arm/mm/cache-v7.S to __armv7_mmu_cache_on in head.S QEMU aborts > somewhere inside the new code. Please see the head.S patch below:
It would be helpful if you said what the abort actually was (ie what instruction do we abort on, what are the fault status/ fault address registers if applicable, etc). (I assume you mean "we send an abort to the guest", not "QEMU's C code calls abort(); if the latter, please provide a backtrace.) thanks -- PMM
