On Fri, Oct 2, 2015 at 11:08 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 2 October 2015 at 18:25, Peter Crosthwaite > <crosthwaitepe...@gmail.com> wrote: >> So my idea here is the CPU input frequency should be a property of the CPU. >> >> Some experimental results confirm that the PMCCNTR on many common ARM >> implementations is directly connected to the input clock and can be >> relied on as a straight free-running counter. I think a genuine >> instruction counter is something else and this timer should be >> independent of any core provider of cycle count. > > Architecturally, the PMCCNTR counter is counting the hardware processor > clock. It's definitely not an instruction counter. (It's also not > counting Processor Element clock cycles, though that only makes a > difference if you have a multi-threaded hw implementation.) It is > generally subject to any hw changes in clock frequency (including if > your WFI/WFE do clock stopping). >
WFI/WFE halting could be easily implemented directly as that, in similar way to EL filtering. > What that means for QEMU I'm not totally sure :-) I think this all points to it being just another normal timer (like those in hw/timer). Regards, Peter > > thanks > -- PMM
