From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Stage-2 MMU translations do not have configurable TBI as
the top byte is always 0 (48-bit IPAs).
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
---
target-arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ec19e68..9ea9719 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6350,7 +6350,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
va_size = 64;
if (el > 1) {
tbi = extract64(tcr->raw_tcr, 20, 1);
- } else {
+ } else if (mmu_idx != ARMMMUIdx_S2NS) {
if (extract64(address, 55, 1)) {
tbi = extract64(tcr->raw_tcr, 38, 1);
} else {
--
1.9.1
