On 8/25/15 22:28, Richard Henderson wrote:
> On 08/25/2015 06:12 AM, Chen Gang wrote:
>>>>
>>>> Consider a bundle like
>>>>
>>>> { add r0, r0, r1 ; exch r2, r0, r3 }
>>>>
>>>> In Chen's implementation, the writeback to r0 would occur before the
>>>> exception, and so the exch would happen to the wrong address. In my
>>>> implementation here, the exception would occur before the writeback, and
>>>> so the result of the add would be discarded.
>>>
>>> We use tmp regs for buffering the r0.
>>>
>>> - calculate x1 pipe, and save result to r0 tmp reg.
>>>
>>
>> Oh, typo, calculate x0 pipe, and save result to r0 tmp reg.
>>
>>> - exch the original r0 and r3 to r2 tmp reg.
>>>
>>> - set exception flag (which will cause exception, later).
>>>
>>> - save the result tmp regs to r0 or r2.
>>>
>>> - gen exception.
>
> Exactly. Now re-read what I wrote and see if you can spot the problem with
> this.
>
OK, thanks. In my memory, originally, we discussed about related things,
you provided several good ideas (temp regs, and gen exceptions ...).
Based on them, I implemented it in this way, hope it is correct.
At present, for gcc testsuite, I met several (10+) pending issues, which
need to be fixed, next. So I guess, there must be still any issues which
we did not find in the current whole tilegx code.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
