On 5/8/10, Artyom Tarasenko <atar4q...@googlemail.com> wrote: > On the real hardware (SS-5, LX) the MMU is not padded, but aliased. > Software shouldn't use aliased addresses, neither should it crash > when it uses (on the real hardware it wouldn't). Using empty_slot > instead of aliasing can help with debugging such accesses.
TurboSPARC Microprocessor User's Manual shows that there are additional pages after the main IOMMU for AFX registers. So this is not board specific, but depends on CPU/IOMMU versions. One approach would be that IOMMU_NREGS would be increased to cover these registers (with the bump in savevm version field) and iommu_init1() should check the version field to see how much MMIO to provide. But in order to avoid the savevm version change, iommu_init1() could just install dummy MMIO (in the TurboSPARC case), if OBP does not care if the read back data matches what has been written earlier. Because from OBP point of view this is identical to what your patch results in, I'd suppose this approach would also work.
