On 20/07/2015 12:53, Efimov Vasily wrote: > This patch improves PAM emulation. > > PAM defines 4 memory access redirection modes. In mode 1 reads are directed to > RAM and writes are directed to PCI. In mode 2 it is contrary. In mode 0 all > access is directed to PCI. In mode 3 it is directed to RAM. Currently all > modes > are emulated using aliases. It is good for modes 0 and 3 but modes 1 and 2 > require more complicated logic. Present API has not needed region type. > > The patch uses ROM-like regions for modes 1 and 2. Each region has I/O > callbacks > to redirect access to destination defined by current mode. Write access is > always redirected by callback. If actual read source is RAM or ROM (it is > common case) then ram_addr of PAM region is set to ram_addr of source region > with offset. Otherwise, when source region is an I/O region, reading is > redirected to source region read callback by PAM region one. > > The reasons of ram_addr modification for read redirection are: > - QEMU cannot execute code outside RAM or ROM (while BIOS tries exactly that); > - it is faster because of TLB is used. > > Redirection is based on address spaces: for PCI and for RAM. QEMU has no ones > so > PAM creates private address spaces with root regions that alias to actual PCI > and RAM regions. > > The memory commit callbacks are used to keep read source and write destination > address spaces and ram_addr up to date. > > Signed-off-by: Efimov Vasily <r...@ispras.ru>
Out of curiosity, would it be necessary to flush the TLB when the PAM registers change? In QEMU, the TLB also has the function of a cache in some sense (because, by pointing to a ram_addr_t, it prevents reads, writes or fetches from going through the slow MMIO path). Paolo
