On 2015-07-19 13:56, Paolo Bonzini wrote: > > > On 19/07/2015 00:20, Benjamin Herrenschmidt wrote: > > + * For BookE, we need in theory 8 MMU modes, which would > > + * reduce performance, so instead, we ignore msr_hv and > > + * will flush on HV context switches. We *could* improve > > + * things a bit if needed by using 4 and 5 as HV and flush > > + * only when HV mode changes AS but that complicates things > > + * as we would need to remember which is the current AS mode > > + * for HV for I and D and split more would be hell. > > + * > > 8 MMU modes wouldn't reduce performance, only 9 would: > > #define CPU_TLB_BITS \ > MIN(8, \ > TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ > (NB_MMU_MODES <= 1 ? 0 : \ > NB_MMU_MODES <= 2 ? 1 : \ > NB_MMU_MODES <= 4 ? 2 : \ > NB_MMU_MODES <= 8 ? 3 : 4)) >
One way to improve this would be to reduce the size of a TLB entry. Currently we store the page address separately for read, write and code. The information is therefore quite redundant. We might want to have only one page address entry and encode if it is allowed for read, write or code in the low bits just like we do for invalid, mmio or dirty. This means the TLB entry can be checked with env->tlb_table[mmu_idx][page_index].ADDR == (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))) | READ/WRITE/CODE) with READ/WRITE/CODE each being a different bit (they can probably even replace invalid). In practice it means one more instruction in the fast path (one or with a 8-bit immediate), but it allows to divide the size of a TLB entry by two on a 64-bit machine. It might be worth a try. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurel...@aurel32.net http://www.aurel32.net
