On 30 June 2015 at 14:07, Peter Maydell <peter.mayd...@linaro.org> wrote: > This patchset enables the TZ support in the GIC for the systems > where we enable TZ support in the CPU. In practice that means > just the "virt" and "vexpress" boards, since all the others > disable the CPU TZ support.
Further playing about with this has raised a couple of interesting issues: (1) we forgot to actually implement the secure physical timer (and we need to fix up the wiring bodge we do in the boards where we assume the physical timer is the NS phys timer) (2) the UEFI firmware for the virt board assumes it is not running in a Secure environment, so is likely to go wrong if we present it with a TZ-aware CPU and GIC. We probably need to default to no-TZ. (This also sort of links in with the wider question of how we tell firmware running on 'virt' about system configurations where some devices are S only.) -- PMM
