On 2015-06-23 16:38, Yongbok Kim wrote:
> Define a new CPU definition supporting MIPS32 Release 6 ISA and
> microMIPS32 Release 6 ISA.
>
> Signed-off-by: Yongbok Kim <yongbok....@imgtec.com>
> ---
> target-mips/translate_init.c | 37 +++++++++++++++++++++++++++++++++++++
> 1 files changed, 37 insertions(+), 0 deletions(-)
>
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index 30605da..ddfaff8 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -424,6 +424,43 @@ static const mips_def_t mips_defs[] =
> .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
> .mmu_type = MMU_TYPE_R4000,
> },
> + {
> + /* A generic CPU supporting MIPS32 Release 6 ISA.
> + FIXME: Support IEEE 754-2008 FP.
> + Eventually this should be replaced by a real CPU model. */
> + .name = "mips32r6-generic",
> + .CP0_PRid = 0x00010000,
> + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
> + (MMU_TYPE_R4000 << CP0C0_MT),
> + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
> + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
> + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
> + (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
> + .CP0_Config2 = MIPS_CONFIG2,
> + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
> + (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
> + (1 << CP0C3_RXI) | (1U << CP0C3_M),
> + .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
> + (3 << CP0C4_IE) | (1U << CP0C4_M),
> + .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB),
> + .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
> + (1 << CP0C5_UFE),
> + .CP0_LLAddr_rw_bitmask = 0,
> + .CP0_LLAddr_shift = 0,
> + .SYNCI_Step = 32,
> + .CCRes = 2,
> + .CP0_Status_rw_bitmask = 0x3058FF1F,
> + .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
> + (1U << CP0PG_RIE),
> + .CP0_PageGrain_rw_bitmask = 0,
> + .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
> + (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
> + (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
> + .SEGBITS = 32,
> + .PABITS = 32,
> + .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
> + .mmu_type = MMU_TYPE_R4000,
> + },
> #if defined(TARGET_MIPS64)
> {
> .name = "R4000",
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
