Public bug reported:
Usually all accesses to coprocessor registers are only possible in PL1
or higher. When accessing a coprocessor register in user mode, QEMU
generates a trap and the PC of the trapping instruction is passed to the
OS with an offset of+ 4. Some coprocessor registers can be configured to
allow access to them in usermode (PL0). The latest qemu-git
(ee09f84e6bf5383a23c9624115c26b72aa1e076c) seems to add an offest of 8
instead of four if such a register is accessed from user mode. This
happens only if the coprocessors register that is accessed might also be
accessed from PL0. In case all accesses to the coprocessor register from
PL0 cause a trap, qemu injects the #UND trap with the correct PC value.
Attached is a small test program that installs a signal handler for
"SIGILL". On a pandaboard the progam prints "Val=0x2 Val2=0x2" whereas
on the latest "qemu-system-arm" the output is : "Val=0x1 Val2=0x2"
Qemu was configured with: "./configure --python=`which python2.7`
--target-list=arm-softmmu"
The test can be compiled with: "gcc -g -static test2.c -o test2"
If further information is needed, feel free to ask.
Regards,
Robert
** Affects: qemu
Importance: Undecided
Status: New
** Attachment added: "test2.c"
https://bugs.launchpad.net/bugs/1463338/+attachment/4411985/+files/test2.c
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https://bugs.launchpad.net/bugs/1463338
Title:
qemu-system-arm injects #UND exception with wrong PC
Status in QEMU:
New
Bug description:
Usually all accesses to coprocessor registers are only possible in PL1
or higher. When accessing a coprocessor register in user mode, QEMU
generates a trap and the PC of the trapping instruction is passed to
the OS with an offset of+ 4. Some coprocessor registers can be
configured to allow access to them in usermode (PL0). The latest qemu-
git (ee09f84e6bf5383a23c9624115c26b72aa1e076c) seems to add an offest
of 8 instead of four if such a register is accessed from user mode.
This happens only if the coprocessors register that is accessed might
also be accessed from PL0. In case all accesses to the coprocessor
register from PL0 cause a trap, qemu injects the #UND trap with the
correct PC value.
Attached is a small test program that installs a signal handler for
"SIGILL". On a pandaboard the progam prints "Val=0x2 Val2=0x2" whereas
on the latest "qemu-system-arm" the output is : "Val=0x1 Val2=0x2"
Qemu was configured with: "./configure --python=`which python2.7`
--target-list=arm-softmmu"
The test can be compiled with: "gcc -g -static test2.c -o test2"
If further information is needed, feel free to ask.
Regards,
Robert
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