On 2 June 2015 at 11:32, Peter Crosthwaite <peter.crosthwa...@xilinx.com> wrote: > On Tue, Jun 2, 2015 at 3:15 AM, Liviu Ionescu <i...@livius.net> wrote: >> similar content is also present in Table B3-1 "ARMv7-M address map", in ARM >> DDI 0403D, "ARMv7-M Architecture Reference Manual". >> >> 0x00000000-0x1FFFFFFF | Code | Typically ROM or flash memory. Memory >> required from address 0x0 to support the vector table for system boot code >> on reset. >> 0x20000000-0x3FFFFFFF | SRAM | SRAM region typically used for on-chip RAM. >> > > The Devil is in the "typically" which means it's not actually specced > on the processor layer. I think the case is reasonable for your > intermediate layer though with a critical mass of vendors opting into > this "typical" case.
Yep. The CPU itself (and the M profile architecture) are opinionated about the memory map layout (much more so than A/R profile), but don't actually insist on it, and the flash/ROM are outside the core proper. -- PMM
