From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Hi,
This is round 3 of our series towards support for EL2 for AArch64. This series depends on Peters target-arm.next. While adding the AArch32 versions of some of these regs I ran into issues with the overly broad definition of TLB_LOCKDOWN. I broke it down somewhat to v7 level. Peter, I noticed a typo in an assert on the target_el series. P1 is a fix for that, feel free to squash into target-arm.next if you like. Comments welcome! Best regards, Edgar v2 -> v3: * Use CP_ACCESS_TRAP_EL2 instead of setting target_el * Add fix for non-EL3 check in assert v1 -> v2: * Drop PAR_EL1 * Add AArch32 mappings of MAIR_EL2 * Add AArch32 mappings of TCR_EL2 * Add AArch32 mappings of SCTLR_EL2 * Add AArch32 mappings of TTBR0_EL2 * Add AArch32 mappings of TPIDR_EL2 * Add AArch32 mappings of CNTHCTL_EL2 * Add AArch32 mappings of CNTVOFF_EL2 * Tag CNTVOFF_EL2 and CNTVOFF as ARM_CP_IO * Rename TLIBALLE2 -> TLBI_ALLE2 * Break down TLB_LOCKDOWN to v7 level Edgar E. Iglesias (15): target-arm: Correct check for non-EL3 target-arm: Break down TLB_LOCKDOWN target-arm: Add MAIR_EL2 target-arm: Add TCR_EL2 target-arm: Add SCTLR_EL2 target-arm: Add TPIDR_EL2 target-arm: Add TTBR0_EL2 target-arm: Add TLBI_ALLE1{IS} target-arm: Add TLBI_ALLE2 target-arm: Add TLBI_VAE2{IS} target-arm: Add CNTVOFF_EL2 target-arm: Add CNTHCTL_EL2 target-arm: Pass timeridx as argument to various timer functions target-arm: Add HYP timer hw/arm/virt: Connect the Hypervisor timer hw/arm/virt.c | 3 + target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 2 + target-arm/cpu.h | 5 +- target-arm/helper.c | 338 +++++++++++++++++++++++++++++++++++++++++++------ target-arm/op_helper.c | 2 +- 6 files changed, 308 insertions(+), 43 deletions(-) -- 1.9.1