On 11 May 2015 at 14:15, Yongbok Kim <yongbok....@imgtec.com> wrote:
> The thing is that the fact misaligned accesses of MSA LD/ST should be allowed
> in R5 cores
> while all other instructions are not allowed.
> Therefore it is required which types of instruction is triggering the
> misaligned accesses.
>
> Initially I tried to fetch the instructions from the
> mips_cpu_do_unaligned_access() callback,
> but if in certain case that the LD/ST address and PC are having same TLB
> indexes it goes wrong.
>
> I also tried to increase mmu_idx to avoid this problem but that requires
> anyway a flag as it is not
> able to pass mmu_idx to cpu_{ld,st}XX_XXX(). (cpu_{ld,st}XX_XXX() are calling
> cpu_mmu_index() to get mmu_idx).
>
> I could use host address directly via {ld,st}xx_p() but then mmio will be
> left alone to be solved.
> Perhaps another flag for the only case of R5 + MSA + MMIO.
>
> I might able to change all the generic load/store macros such as
> cpu_ldst_template.h and
> softmmu_template.h to pass the misalignment information.
> However that would be a huge work impacting all the architectures.
Ideally it would be nice to have support in TCG so that a frontend
could output a TCG load/store op with a flag for "unaligned access
OK" or not. ARM also has this issue of some load/stores wanting to
do alignment traps and some not.
-- PMM
