On 7 April 2015 at 10:32, Michael S. Tsirkin <m...@redhat.com> wrote:
> On Tue, Apr 07, 2015 at 10:19:22AM +0100, Peter Maydell wrote:
>> On 7 April 2015 at 03:43, Shannon Zhao <zhaoshengl...@huawei.com> wrote:
>> > The dts node is:
>> > ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000
>> > 0x2000000 0x0 0x10000000 0x0 0x10000000 0x0
>> > 0x2eff0000>;
>> > reg = <0x0 0x3f000000 0x0 0x1000000>;
>> > bus-range = <0x0 0xf>;
>> >
>> > The ACPI table entry:
>> > Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base
>> > Address
>> > {
>> > Return (0x3F000000)
>> > }
>> > Method (_CRS, 0, NotSerialized) // _CRS: Current Resource
>> > Settings
>> > {
>> > Name (RBUF, ResourceTemplate ()
>> > {
>> > WordBusNumber (ResourceProducer, MinFixed, MaxFixed,
>> > PosDecode,
>> > 0x0000, // Granularity
>> > 0x0000, // Range Minimum
>> > 0x000F, // Range Maximum
>> > 0x0000, // Translation Offset
>> > 0x0010, // Length
>> > ,, )
>> > DWordMemory (ResourceProducer, PosDecode, MinFixed,
>> > MaxFixed, Cacheable, ReadWrite,
>>
>> Is this claiming that the non-cacheable PCI MMIO region is cacheable?
>> If so that isn't right...
>
> I suspect that's fine.
> Some parts of MMIO might be cacheable. This really depends on the
> device
No, this is the PCI "non-cacheable MMIO" window. (We don't have
a cacheable MMIO window on this board). In the DTB we advertise
it as non-cacheable, and we should do the same in ACPI.
-- PMM
