Hi,
On Mon, Mar 23, 2015 at 8:05 PM, Peter Crosthwaite
<peter.crosthwa...@xilinx.com> wrote:
> Similar to a53, but with different L1 I cache policy, phys addr size and
^^^
I guess a57 :)
ozaki-r
> different cache geometries. The cache sizes is implementation
> configurable, but use these values (from Xilinx MPSoC) as a default
> until cache size configurability is added.
>
> Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
> Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
> ---
> Changed since v2:
> Added dtb compatible string
>
> target-arm/cpu64.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index 3eb58c6..728d9a7 100644
> --- a/target-arm/cpu64.c
> +++ b/target-arm/cpu64.c
> @@ -149,6 +149,21 @@ static void aarch64_a57_initfn(Object *obj)
> cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
> }
>
> +static void aarch64_a53_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + aarch64_axx_initfn(cpu);
> +
> + cpu->dtb_compatible = "arm,cortex-a53";
> + cpu->midr = 0x410fd034;
> + cpu->ctr = 0x84448004; /* L1Ip = VIPT */
> + cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
> + cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
> + cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
> + cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
> +}
> +
> #ifdef CONFIG_USER_ONLY
> static void aarch64_any_initfn(Object *obj)
> {
> @@ -176,6 +191,7 @@ typedef struct ARMCPUInfo {
>
> static const ARMCPUInfo aarch64_cpus[] = {
> { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
> + { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
> #ifdef CONFIG_USER_ONLY
> { .name = "any", .initfn = aarch64_any_initfn },
> #endif
> --
> 2.3.1.2.g90df61e.dirty
>
