Add a new function arm_generate_memory_dtb which is used to
generate memory dtb according to NUMA topology and set the
NUMA topology property of every cpu.
Signed-off-by: Shannon Zhao <zhaoshengl...@huawei.com>
---
hw/arm/boot.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++--
1 files changed, 77 insertions(+), 3 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 52ebd8b..a39b2b4 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -312,6 +312,82 @@ static void set_kernel_args_old(const struct arm_boot_info
*info)
}
}
+/*
+ * arm_generate_memory_dtb() - generate memory dtb according to NUMA topology
+ * @fdt: the pointer to device tree
+ * @binfo: struct describing the boot environment
+ * @acells: address-cells of device tree
+ * @scells: size-cells of device tree
+ *
+ * Returns:0 success,
+ * -1 on errors.
+ *
+ */
+static int arm_generate_memory_dtb(void *fdt, const struct arm_boot_info
*binfo,
+ uint32_t acells, uint32_t scells)
+{
+ CPUState *cpu;
+ int i = 0;
+
+ if (!nb_numa_nodes) {
+ qemu_fdt_add_subnode(fdt, "/memory");
+ qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
+ return qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg",
+ acells, binfo->loader_start,
+ scells, binfo->ram_size);
+ }
+
+ struct {
+ uint64_t mem_map[6];
+ uint64_t cpu_map[6];
+ } numa_map;
+
+ hwaddr mem_base = binfo->loader_start;
+
+ for (i = 0; i < nb_numa_nodes; i++) {
+ /* Generate mem_map */
+ char *nodename;
+ nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
+ qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
+ acells, mem_base,
+ scells, numa_info[i].node_mem - 1);
+ numa_map.mem_map[0] = 0x1;
+ numa_map.mem_map[1] = i;
+ numa_map.mem_map[2] = 0x1;
+ numa_map.mem_map[3] = 0x0;
+ numa_map.mem_map[4] = 0x1;
+ numa_map.mem_map[5] = 0xffff;
+
+ qemu_fdt_setprop_sized_cells_from_array(fdt, nodename,
+ "arm,associativity", 3, numa_map.mem_map);
+
+ mem_base += numa_info[i].node_mem;
+ g_free(nodename);
+
+ /* Generate cpu_map */
+ CPU_FOREACH(cpu) {
+ if (test_bit(cpu->cpu_index, numa_info[i].node_cpu)) {
+ numa_map.cpu_map[0] = 0x1;
+ numa_map.cpu_map[1] = i;
+ numa_map.cpu_map[2] = 0x1;
+ numa_map.cpu_map[3] = 0x0;
+ numa_map.cpu_map[4] = 0x1;
+ numa_map.cpu_map[5] = cpu->cpu_index;
+ nodename = g_strdup_printf("/cpus/cpu@%d", cpu->cpu_index);
+ qemu_fdt_setprop_sized_cells_from_array(fdt, nodename,
+ "arm,associativity", 3, numa_map.cpu_map);
+ g_free(nodename);
+ }
+ }
+ }
+ qemu_fdt_setprop_sized_cells(fdt, "/",
+ "arm,associativity-reference-points", 1, 0, 1, 1);
+
+ return 0;
+}
+
/**
* load_dtb() - load a device tree binary image into memory
* @addr: the address to load the image at
@@ -387,9 +463,7 @@ static int load_dtb(hwaddr addr, const struct arm_boot_info
*binfo,
goto fail;
}
- rc = qemu_fdt_setprop_sized_cells(fdt, "/memory", "reg",
- acells, binfo->loader_start,
- scells, binfo->ram_size);
+ rc = arm_generate_memory_dtb(fdt, binfo, acells, scells);
if (rc < 0) {
fprintf(stderr, "couldn't set /memory/reg\n");
goto fail;
--
1.7.1
