This patch series introduces rudimentary support for the Transactional Memory (TM) feature of Power ISA V2.07. In a nutshell, software uses the feature by initiating a transaction via the tbegin instruction. Hardware then accumulates storage accesses until the transaction is committed via the tend instruction). At this point, either the instruction completes and all storage accesses are atomic with respect to other processors; or the transaction fails and processor state reverts to the point of tbegin. Transaction success or failure is recorded in CR[0] and the instruction immediately following tbegin is expected to inspect this field and provide an error path to properly handle failure.
Accurately emulating such a feature in QEMU is quite difficult. Instead, the approach taken here simply fails the transaction at the point of tbegin and thus immediately takes software down the error handlling path. As such, this can be considered a toleration mode for any software that utilizes the TM feature. Valgrind has taken a similar approach. There are no immediate plans to implement a more sophisticated model. Currently, Power8 is the only Power processor that supports TM. Tom Musta (9): target-ppc: Introduce Instruction Type for Transactional Memory target-ppc: Introduce Feature Flag for Transactional Memory target-ppc: Introduce tm_enabled Bit to CPU State target-ppc: Power8 Supports Transactional Memory target-ppc: Introduce TEXASRU Bit Fields target-ppc: Introduce tbegin target-ppc: Introduce TM Noops target-ppc: Introduce tcheck target-ppc: Introduce Privileged TM Noops target-ppc/cpu.h | 26 ++++++++++- target-ppc/helper.h | 2 + target-ppc/mem_helper.c | 22 ++++++++ target-ppc/translate.c | 113 +++++++++++++++++++++++++++++++++++++++++++ target-ppc/translate_init.c | 5 +- 5 files changed, 165 insertions(+), 3 deletions(-)
