On 15/12/2014 14:23, Peter Maydell wrote: > > What are the intended semantics for reads/writes from the outside world? > > Should they cause the ll/sc pair to retry or not? > Assuming that by "outside world" you mean "some other CPU in this > cluster" [in ARM-speak, some other observer in the same shareability > domain]: writes should. Reads should not.
No, I mean from DMA. Other CPU of course need to abort reads/writes. The CPU that executes LL can invalidate the physical address on all other CPUs' TLBs. Attempts to write to that address then would fill the TLB entry with the new TLB_LL bit. Paolo
