Hi Yongbok, On 29/10/14 13:55, Yongbok Kim wrote: > On 24/10/2014 13:42, Leon Alrae wrote: >> case EXCP_TLBRI: >> cause = 19; >> + update_badinstr = 1; >> goto set_EPC; >> case EXCP_TLBXI: >> cause = 20; > > TLBXI requires updating the register.
TLBXI exception can be generated by instruction fetch or MIPS16 PC-relative load. IIUC if TLBXI is caused by instruction fetch the value stored in BadInstr is unpredictable as valid instruction word is not available (the same case as TLB Refill - Instruction Fetch). Therefore in context of Release 6 the implementation is correct. As far as MIPS16 is concerned, this is similar limitation which we discussed for patch #4 (i.e. MIPS16 PC-relative load should ignore RI bit). Regards, Leon
