On Fri, Oct 10, 2014 at 8:57 PM, Peter Maydell <peter.mayd...@linaro.org> wrote:
> The ARM ARM requires that the FPINST and FPINST2 VFP control
> registers are not accessible to code at EL0. We were already
> correctly implementing this for reads of these registers; add
> the missing check for the write code path.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnog...@gmail.com>
Thanks,
Laurent
> ---
> target-arm/translate.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 8a2994f..d8ee2e4 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -3199,6 +3199,9 @@ static int disas_vfp_insn(CPUARMState * env,
> DisasContext *s, uint32_t insn)
> break;
> case ARM_VFP_FPINST:
> case ARM_VFP_FPINST2:
> + if (IS_USER(s)) {
> + return 1;
> + }
> tmp = load_reg(s, rd);
> store_cpu_field(tmp, vfp.xregs[rn]);
> break;
> --
> 1.9.1
>
