On 10 September 2014 08:02, Ard Biesheuvel <ard.biesheu...@linaro.org> wrote:
> From: Rob Herring <rob.herr...@linaro.org>
>
> Add the infrastructure to handle and emulate hvc and smc exceptions.
> This will enable emulation of things such as PSCI calls. This commit
> does not change the behavior and will exit with unknown exception.
>
> Signed-off-by: Rob Herring <rob.herr...@linaro.org>
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
> diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
> index 89b913ee9396..1f8072ab141b 100644
> --- a/target-arm/helper-a64.c
> +++ b/target-arm/helper-a64.c
> @@ -485,6 +485,22 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
> case EXCP_FIQ:
> addr += 0x100;
> break;
> + case EXCP_HVC:
> + if (arm_cpu_do_hvc(cs)) {
> + return;
> + }
> + /* Treat as unallocated encoding */
> + qemu_log_mask(LOG_GUEST_ERROR, "HVC not implemented on this CPU\n");
> + env->exception.syndrome = syn_uncategorized();
> + break;
> + case EXCP_SMC:
> + if (arm_cpu_do_smc(cs)) {
> + return;
> + }
> + /* Treat as unallocated encoding */
> + qemu_log_mask(LOG_GUEST_ERROR, "SMC not implemented on this CPU\n");
> + env->exception.syndrome = syn_uncategorized();
> + break;
Looking again at this there are some issues with this,
notably that we don't do anything to ensure that the PC
is pointing at the instruction we're claiming to be UNDEF
rather than just after it.
The best approach seems to me to be to figure out at
translate time whether we're going to call this SMC
UNDEF or not.
We also seem to only generate the SMC and HVC exception
if the CPU has the FEATURE_EL2/3 bit set, which confuses
me because our CPUs don't set that and so I'm not sure
how this works at all...
I think the best way to fix this is going to be to rebase
this on top of Edgar's EL2/EL3 support patches, which
already deal with most of those problems (albeit only
for AArch64 currently). I'll do that and send out a
fixed version.
thanks
-- PMM
