On 13 September 2014 05:29, Edgar E. Iglesias <edgar.igles...@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
> ---
> target-arm/cpu.h | 19 ++++++++++++++++++-
> target-arm/helper.c | 35 +++++++++++++++++++++++++++++++++--
> 2 files changed, 51 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 36507f9..c69d471 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -172,7 +172,6 @@ typedef struct CPUARMState {
> uint64_t c1_sys; /* System control register. */
> uint64_t c1_coproc; /* Coprocessor access register. */
> uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
> - uint32_t c1_scr; /* secure config register. */
> uint64_t ttbr0_el1; /* MMU translation table base 0. */
> uint64_t ttbr1_el1; /* MMU translation table base 1. */
> uint64_t c2_control; /* MMU translation table base control. */
> @@ -185,6 +184,7 @@ typedef struct CPUARMState {
> uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
> uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
> uint64_t hcr_el2; /* Hypervisor configuration register */
> + uint64_t scr_el3; /* Secure configuration register. */
> uint32_t ifsr_el2; /* Fault status registers. */
> uint64_t esr_el[4];
> uint32_t c6_region[8]; /* MPU base/size registers. */
> @@ -873,8 +899,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
> .resetvalue = 0 },
> { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
> - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
> - .resetvalue = 0, },
> + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
> + .resetvalue = 0, .writefn = scr_write },
Still wrong, I'm afraid. For a 32 bit register with a 64
bit struct field you have to use offsetoflow32(), otherwise
you'll get the wrong half on bigendian hosts.
thanks
-- PMM
