On Tue, Sep 16, 2014 at 1:01 AM, Peter Crosthwaite
<peter.crosthwa...@xilinx.com> wrote:
> On Sun, Sep 14, 2014 at 6:18 PM, Alistair Francis <alistai...@gmail.com>
> wrote:
>> This patch adds the stm32f205 timers: TIM2, TIM3, TIM4 and TIM5
>> to QEMU.
>>
>> Signed-off-by: Alistair Francis <alistai...@gmail.com>
>> ---
>> Changes from RFC:
>> - Small changes to functionality and style. Thanks to Peter C
>> - Rename to make the timer more generic
>> - Split the config settings to device level
>>
>> default-configs/arm-softmmu.mak | 1 +
>> hw/timer/Makefile.objs | 1 +
>> hw/timer/stm32f205_timer.c | 305
>> +++++++++++++++++++++++++++++++++++++
>> include/hw/timer/stm32f205_timer.h | 97 ++++++++++++
>> 4 files changed, 404 insertions(+)
>> create mode 100644 hw/timer/stm32f205_timer.c
>> create mode 100644 include/hw/timer/stm32f205_timer.h
>>
>> diff --git a/default-configs/arm-softmmu.mak
>> b/default-configs/arm-softmmu.mak
>> index f3513fa..cf23b24 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -78,6 +78,7 @@ CONFIG_NSERIES=y
>> CONFIG_REALVIEW=y
>> CONFIG_ZAURUS=y
>> CONFIG_ZYNQ=y
>> +CONFIG_STM32F205_TIMER=y
>>
>> CONFIG_VERSATILE_PCI=y
>> CONFIG_VERSATILE_I2C=y
>> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
>> index 2c86c3d..6c1661e 100644
>> --- a/hw/timer/Makefile.objs
>> +++ b/hw/timer/Makefile.objs
>> @@ -17,6 +17,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
>> common-obj-$(CONFIG_IMX) += imx_gpt.o
>> common-obj-$(CONFIG_LM32) += lm32_timer.o
>> common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
>> +common-obj-$(CONFIG_STM32F205_TIMER) += stm32f205_timer.o
>>
>
> The grouping of this with the random SoC configs is a little strange.
> I suggest just creating your own blank-line separated grouping like
> with allwinner currently at the bottom.
>
Will fix
>> obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
>> obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
>> diff --git a/hw/timer/stm32f205_timer.c b/hw/timer/stm32f205_timer.c
>> new file mode 100644
>> index 0000000..c4a84eb
>> --- /dev/null
>> +++ b/hw/timer/stm32f205_timer.c
>> @@ -0,0 +1,305 @@
>> +/*
>> + * STM32F205 Timer
>> + *
>> + * Copyright (c) 2014 Alistair Francis <alist...@alistair23.me>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> copy
>> + * of this software and associated documentation files (the "Software"), to
>> deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included
>> in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "hw/timer/stm32f205_timer.h"
>> +
>> +#ifndef STM_TIMER_ERR_DEBUG
>> +#define STM_TIMER_ERR_DEBUG 0
>> +#endif
>> +
>> +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> + if (STM_TIMER_ERR_DEBUG >= lvl) { \
>> + qemu_log("stm32f205_timer: %s:" fmt, __func__, ## args); \
>> + } \
>> +} while (0);
>> +
>> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>> +
>> +static void stm32f205_timer_interrupt(void *opaque)
>> +{
>> + STM32f205TimerState *s = opaque;
>> +
>> + DB_PRINT("Interrupt in: %s\n", __func__);
>> +
>> + if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) {
>> + s->tim_sr |= 1;
>> + qemu_irq_pulse(s->irq);
>> + }
>> +}
>> +
>> +static void stm32f205_timer_set_alarm(STM32f205TimerState *s)
>> +{
>> + uint32_t ticks;
>> + int64_t now;
>> +
>> + DB_PRINT("Alarm raised in: %s at 0x%x\n", __func__, s->tim_cr1);
>> +
>
> You already %s __func__ as part of the DB_PRINT so no need for the dup.
>
Yep
>> + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
>> + ticks = s->tim_arr - (s->tick_offset + (now / get_ticks_per_sec())) *
>> + (s->tim_psc + 1);
>
> I'm having trouble with the dimensional analysis of this. tim_arr is
> in terms of counter cycles but ticks must be in terms of ns (with it's
> addition to now below). So you have equating of cycles to time
> implying fixed frequency scaling. However you attempt to model the
> prescaling with your use of tim_psc?
>
I think I have fixed it, will update in the respin.
>> +
>> + DB_PRINT("Alarm set in %d ticks\n", ticks);
>> +
>> + if (ticks == 0) {
>> + timer_del(s->timer);
>> + stm32f205_timer_interrupt(s);
>> + } else {
>> + timer_mod(s->timer, (now + (int64_t) ticks));
>> + DB_PRINT("Wait Time: %u\n", (uint32_t) (now + ticks));
>
> Better to use a PRId64 and drop the cast so the debug messages still
> look good after now rolls over 4G.
Will fix
>
>> + }
>> +}
>> +
>> +static void stm32f205_timer_reset(DeviceState *dev)
>> +{
>> + STM32f205TimerState *s = STM32F205TIMER(dev);
>> +
>> + s->tim_cr1 = 0;
>> + s->tim_cr2 = 0;
>> + s->tim_smcr = 0;
>> + s->tim_dier = 0;
>> + s->tim_sr = 0;
>> + s->tim_egr = 0;
>> + s->tim_ccmr1 = 0;
>> + s->tim_ccmr2 = 0;
>> + s->tim_ccer = 0;
>> + s->tim_cnt = 0;
>> + s->tim_psc = 0;
>> + s->tim_arr = 0;
>> + s->tim_ccr1 = 0;
>> + s->tim_ccr2 = 0;
>> + s->tim_ccr3 = 0;
>> + s->tim_ccr4 = 0;
>> + s->tim_dcr = 0;
>> + s->tim_dmar = 0;
>> + s->tim_or = 0;
>> +}
>> +
>> +static uint64_t stm32f205_timer_read(void *opaque, hwaddr offset,
>> + unsigned size)
>> +{
>> + STM32f205TimerState *s = opaque;
>> +
>> + DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset);
>> +
>> + switch (offset) {
>> + case TIM_CR1:
>> + return s->tim_cr1;
>> + case TIM_CR2:
>> + return s->tim_cr2;
>> + case TIM_SMCR:
>> + return s->tim_smcr;
>> + case TIM_DIER:
>> + return s->tim_dier;
>> + case TIM_SR:
>> + return s->tim_sr;
>> + case TIM_EGR:
>> + return s->tim_egr;
>> + case TIM_CCMR1:
>> + return s->tim_ccmr1;
>> + case TIM_CCMR2:
>> + return s->tim_ccmr2;
>> + case TIM_CCER:
>> + return s->tim_ccer;
>> + case TIM_CNT:
>> + return s->tim_cnt;
>> + case TIM_PSC:
>> + return s->tim_psc;
>> + case TIM_ARR:
>> + return s->tim_arr;
>> + case TIM_CCR1:
>> + return s->tim_ccr1;
>> + case TIM_CCR2:
>> + return s->tim_ccr2;
>> + case TIM_CCR3:
>> + return s->tim_ccr3;
>> + case TIM_CCR4:
>> + return s->tim_ccr4;
>> + case TIM_DCR:
>> + return s->tim_dcr;
>> + case TIM_DMAR:
>> + return s->tim_dmar;
>> + case TIM_OR:
>> + return s->tim_or;
>> + default:
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "STM32F205_timer_write: Bad offset %x\n", (int)
>> offset);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void stm32f205_timer_write(void *opaque, hwaddr offset,
>> + uint64_t val64, unsigned size)
>> +{
>> + STM32f205TimerState *s = opaque;
>> + uint32_t value = val64;
>> +
>> + DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset);
>> +
>> + switch (offset) {
>> + case TIM_CR1:
>> + s->tim_cr1 = value;
>> + return;
>> + case TIM_CR2:
>> + s->tim_cr2 = value;
>> + return;
>> + case TIM_SMCR:
>> + s->tim_smcr = value;
>> + return;
>> + case TIM_DIER:
>> + s->tim_dier = value;
>> + return;
>> + case TIM_SR:
>> + s->tim_sr &= value;
>
> Took some getting my head around the &= but TRM does say set by
> hardware and cleared by software. Worth a comment?
I'll add a comment.
>
>> + stm32f205_timer_set_alarm(s);
>
> This doesn't look right. I think you might be trying to implement
> periodic timing by reloading when the guest clears the ISR. This is
> guest dependent and will also lose time - unless the TRM says that
> timer halts based on ISR? (which I would find quite strange).
>
> The reload logic should probably happen from the timer callback itself.
Ok, I have moved it to the interrupt function.
>
> You may need to look into some of the other timers and how they
> implement accurate periodic timing. You can look at ptimer based
> implementations of which there a fair few. I recently did some work on
> arm_mptimer which is a periodic capable timer that uses regular QEMU
> timers which I consider a good simple example of a QEMU timer that
> doesn't use ptimer.
>
>> + return;
>> + case TIM_EGR:
>> + s->tim_egr = value;
>> + if (s->tim_egr & 1) {
>> + /* Re-init the counter */
>> + stm32f205_timer_reset(DEVICE(s));
>> + }
>> + return;
>> + case TIM_CCMR1:
>> + s->tim_ccmr1 = value;
>> + return;
>> + case TIM_CCMR2:
>> + s->tim_ccmr2 = value;
>> + return;
>> + case TIM_CCER:
>> + s->tim_ccer = value;
>> + return;
>> + case TIM_CNT:
>> + s->tim_cnt = value;
>> + stm32f205_timer_set_alarm(s);
>> + return;
>> + case TIM_PSC:
>> + s->tim_psc = value;
>> + return;
>> + case TIM_ARR:
>> + s->tim_arr = value;
>> + stm32f205_timer_set_alarm(s);
>> + return;
>> + case TIM_CCR1:
>> + s->tim_ccr1 = value;
>> + return;
>> + case TIM_CCR2:
>> + s->tim_ccr2 = value;
>> + return;
>> + case TIM_CCR3:
>> + s->tim_ccr3 = value;
>> + return;
>> + case TIM_CCR4:
>> + s->tim_ccr4 = value;
>> + return;
>> + case TIM_DCR:
>> + s->tim_dcr = value;
>> + return;
>> + case TIM_DMAR:
>> + s->tim_dmar = value;
>> + return;
>> + case TIM_OR:
>> + s->tim_or = value;
>> + return;
>> + default:
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "STM32F205_timer_write: Bad offset %x\n", (int)
>> offset);
>
> Missed a HWADDR_PRIx.
>
>> + }
>> +}
>> +
>> +static const MemoryRegionOps stm32f205_timer_ops = {
>> + .read = stm32f205_timer_read,
>> + .write = stm32f205_timer_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> +};
>> +
>> +static void stm32f205_timer_init(Object *obj)
>> +{
>> + STM32f205TimerState *s = STM32F205TIMER(obj);
>> + struct tm tm;
>> +
>> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
>> +
>> + memory_region_init_io(&s->iomem, obj, &stm32f205_timer_ops, s,
>> + "stm32f205_timer", 0x2000);
>> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
>> +
>> + qemu_get_timedate(&tm, 0);
>> + s->tick_offset = mktimegm(&tm) -
>> + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / get_ticks_per_sec();
>> +
>
> This is still trying to be an RTC of sorts. You don't need the
> mktimegm stuff. I think you need to refactor tick_offset as according
> to this it is in terms of seconds, but that doesn't make a lot of
> sense for this timer which should trade in high frequency clock cycles
> or ns I think.
I forgot to take that out, will removed.
Thanks,
Alistair
>
> Regards,
> Peter
>
>> + s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f205_timer_interrupt,
>> s);
>> +}
>> +
>> +static const VMStateDescription vmstate_stm32f205_timer = {
>> + .name = "stm32f205_timer",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT32(tick_offset_vmstate, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_cr1, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_cr2, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_smcr, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_dier, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_sr, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_egr, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_ccmr1, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_ccmr1, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_ccer, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_cnt, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_psc, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_arr, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_ccr1, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_ccr2, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_ccr3, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_ccr4, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_dcr, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_dmar, STM32f205TimerState),
>> + VMSTATE_UINT32(tim_or, STM32f205TimerState),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +static void stm32f205_timer_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->vmsd = &vmstate_stm32f205_timer;
>> + dc->reset = stm32f205_timer_reset;
>> +}
>> +
>> +static const TypeInfo stm32f205_timer_info = {
>> + .name = TYPE_STM32F205_TIMER,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(STM32f205TimerState),
>> + .instance_init = stm32f205_timer_init,
>> + .class_init = stm32f205_timer_class_init,
>> +};
>> +
>> +static void stm32f205_timer_register_types(void)
>> +{
>> + type_register_static(&stm32f205_timer_info);
>> +}
>> +
>> +type_init(stm32f205_timer_register_types)
>> diff --git a/include/hw/timer/stm32f205_timer.h
>> b/include/hw/timer/stm32f205_timer.h
>> new file mode 100644
>> index 0000000..c26ae57
>> --- /dev/null
>> +++ b/include/hw/timer/stm32f205_timer.h
>> @@ -0,0 +1,97 @@
>> +/*
>> + * STM32F205 Timer
>> + *
>> + * Copyright (c) 2014 Alistair Francis <alist...@alistair23.me>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> copy
>> + * of this software and associated documentation files (the "Software"), to
>> deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included
>> in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#ifndef HW_STM_TIMER_H
>> +#define HW_STM_TIMER_H
>> +
>> +#include "hw/sysbus.h"
>> +#include "qemu/timer.h"
>> +#include "sysemu/sysemu.h"
>> +
>> +#define TIM_CR1 0x00
>> +#define TIM_CR2 0x04
>> +#define TIM_SMCR 0x08
>> +#define TIM_DIER 0x0C
>> +#define TIM_SR 0x10
>> +#define TIM_EGR 0x14
>> +#define TIM_CCMR1 0x18
>> +#define TIM_CCMR2 0x1C
>> +#define TIM_CCER 0x20
>> +#define TIM_CNT 0x24
>> +#define TIM_PSC 0x28
>> +#define TIM_ARR 0x2C
>> +#define TIM_CCR1 0x34
>> +#define TIM_CCR2 0x38
>> +#define TIM_CCR3 0x3C
>> +#define TIM_CCR4 0x40
>> +#define TIM_DCR 0x48
>> +#define TIM_DMAR 0x4C
>> +#define TIM_OR 0x50
>> +
>> +#define TIM_CR1_CEN 1
>> +
>> +#define TIM_CCER_CC2E (1 << 4)
>> +#define TIM_CCMR1_OC2M2 (1 << 14)
>> +#define TIM_CCMR1_OC2M1 (1 << 13)
>> +
>> +#define TIM_DIER_UIE 1
>> +
>> +#define TYPE_STM32F205_TIMER "stm32f205-timer"
>> +#define STM32F205TIMER(obj) OBJECT_CHECK(STM32f205TimerState, \
>> + (obj), TYPE_STM32F205_TIMER)
>> +
>> +typedef struct STM32f205TimerState {
>> + /* <private> */
>> + SysBusDevice parent_obj;
>> +
>> + /* <public> */
>> + MemoryRegion iomem;
>> + QEMUTimer *timer;
>> + qemu_irq irq;
>> +
>> + uint32_t tick_offset_vmstate;
>> + uint32_t tick_offset;
>> +
>> + uint32_t tim_cr1;
>> + uint32_t tim_cr2;
>> + uint32_t tim_smcr;
>> + uint32_t tim_dier;
>> + uint32_t tim_sr;
>> + uint32_t tim_egr;
>> + uint32_t tim_ccmr1;
>> + uint32_t tim_ccmr2;
>> + uint32_t tim_ccer;
>> + uint32_t tim_cnt;
>> + uint32_t tim_psc;
>> + uint32_t tim_arr;
>> + uint32_t tim_ccr1;
>> + uint32_t tim_ccr2;
>> + uint32_t tim_ccr3;
>> + uint32_t tim_ccr4;
>> + uint32_t tim_dcr;
>> + uint32_t tim_dmar;
>> + uint32_t tim_or;
>> +} STM32f205TimerState;
>> +
>> +#endif
>> --
>> 1.9.1
>>
>>
