On 9/15/2014 10:03 AM, Paolo Bonzini wrote:
> PowerPC TCG flushes the TLB on every IR/DR change, which basically
> means on every user<->kernel context switch. Encode IR/DR in the
> MMU index.
>
> This brings the number of TLB flushes down from ~900000 to ~50000
> for starting up the Debian installer, which is in line with x86
> and gives a ~10% performance improvement.
>
> Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
> ---
> target-ppc/cpu.h | 7 ++-----
> target-ppc/excp_helper.c | 3 ---
> target-ppc/helper_regs.h | 11 ++++++-----
> 3 files changed, 8 insertions(+), 13 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index b64c652..c29ce3b 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -922,7 +922,8 @@ struct ppc_segment_page_sizes {
>
>
> /*****************************************************************************/
> /* The whole PowerPC CPU context */
> -#define NB_MMU_MODES 3
> +#define NB_MMU_MODES 12
> +#define MMU_USER_IDX 3 /* PR=IR=DR=1 */
This doesn't build for me:
CC ppc64-softmmu/tcg/tcg.o
In file included from /bghome/tmusta/powerisa/qemu/qemu/tcg/tcg.c:264:
/bghome/tmusta/powerisa/qemu/qemu/tcg/ppc/tcg-target.c: In function
?tcg_out_tlb_read?:
/bghome/tmusta/powerisa/qemu/qemu/tcg/ppc/tcg-target.c:1394: error: size of
array ?qemu_build_bug_on__1396? is negative
make[1]: *** [tcg/tcg.o] Error 1
make: *** [subdir-ppc64-softmmu] Error 2
which correlates with this:
1389 /* Compensate for very large offsets. */
1390 if (add_off >= 0x8000) {
1391 /* Most target env are smaller than 32k; none are larger than
64k.
1392 Simplify the logic here merely to offset by 0x7ff0, giving
us a
1393 range just shy of 64k. Check this assumption. */
1394 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
1395 tlb_table[NB_MMU_MODES - 1][1])
1396 > 0x7ff0 + 0x7fff);
1397 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0));
1398 base = TCG_REG_TMP1;
1399 cmp_off -= 0x7ff0;
1400 add_off -= 0x7ff0;
1401 }
>
> #define PPC_CPU_OPCODES_LEN 0x40
>
> @@ -1231,10 +1232,6 @@ static inline CPUPPCState *cpu_init(const char
> *cpu_model)
> #define cpu_list ppc_cpu_list
>
> /* MMU modes definitions */
> -#define MMU_MODE0_SUFFIX _user
> -#define MMU_MODE1_SUFFIX _kernel
> -#define MMU_MODE2_SUFFIX _hypv
> -#define MMU_USER_IDX 0
> static inline int cpu_mmu_index (CPUPPCState *env)
> {
> return env->mmu_idx;
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index 922e86d..96ad9d7 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -623,9 +623,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
>
> if (env->spr[SPR_LPCR] & LPCR_AIL) {
> new_msr |= (1 << MSR_IR) | (1 << MSR_DR);
> - } else if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
> - /* If we disactivated any translation, flush TLBs */
> - tlb_flush(cs, 1);
> }
>
> #ifdef TARGET_PPC64
> diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
> index 271fddf..23b8ded 100644
> --- a/target-ppc/helper_regs.h
> +++ b/target-ppc/helper_regs.h
> @@ -41,12 +41,15 @@ static inline void hreg_swap_gpr_tgpr(CPUPPCState *env)
>
> static inline void hreg_compute_mem_idx(CPUPPCState *env)
> {
> + int high;
> +
> /* Precompute MMU index */
> if (msr_pr == 0 && msr_hv != 0) {
> - env->mmu_idx = 2;
> + high = 2;
> } else {
> - env->mmu_idx = 1 - msr_pr;
> + high = 1 - msr_pr;
> }
> + env->mmu_idx = (high << 2) | (msr_ir << 1) | msr_dr;
> }
>
> static inline void hreg_compute_hflags(CPUPPCState *env)
> @@ -56,7 +59,7 @@ static inline void hreg_compute_hflags(CPUPPCState *env)
> /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */
> hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) |
> (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) |
> - (1 << MSR_LE) | (1 << MSR_VSX);
> + (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR);
> hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB;
> hreg_compute_mem_idx(env);
> env->hflags = env->msr & hflags_mask;
> @@ -82,8 +85,6 @@ static inline int hreg_store_msr(CPUPPCState *env,
> target_ulong value,
> }
> if (((value >> MSR_IR) & 1) != msr_ir ||
> ((value >> MSR_DR) & 1) != msr_dr) {
> - /* Flush all tlb when changing translation mode */
> - tlb_flush(cs, 1);
> excp = POWERPC_EXCP_NONE;
> cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
> }
>
