On 1 September 2014 19:34, David Hoover <s...@boiteauxlettres.sent.at> wrote:
> Hi,
>
> It seems that interrupts are not disabled by CPSIE instruction. The
> current code apparently ignores (daif&PSTATE_I) for Cortex-M. The patch
> below is basically identical to the patch that was attached to the
> following message:
>
> https://lists.gnu.org/archive/html/qemu-devel/2011-06/msg00513.html
Thanks for the prod on this one. I've finally got round to
investigating this to the point of deciding that this change
is OK (though our interrupt handling on M profile is still
way different from what the architecture says it should be).
I've applied this to target-arm.next, with an improved
commit message:
cpu-exec.c: Allow disabling of IRQs on ARM Cortex-M CPUs
Correct an error in the logic for deciding whether we can
take an IRQ interrupt which meant that on M profile cores
it was never possible to disable them.
The design here is still bogus in that M profile doesn't
have separate "IRQ" and "FIQ", which are an A/R profile
concept; we should ideally implement the proper priority
based scheme.
Signed-off-by: David Hoover <s...@boiteauxlettres.sent.at>
[PMM: Wrote a proper commit message]
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
-- PMM
