On Tue, 17 Jun 2014, Alexander Graf wrote:
http://goliat.eik.bme.hu/~balaton/oftest/results/
The results show that the stwx instruction with reserved bit set does not
change status bits and does not generate an exception on any CPU tested
(G3 and G4) so it is most probably just ignored as we thought.
[adding qemu-ppc and tom to CC]
Tom already commented on this. Is there a pattern that matches all the
indexed load/store instructions or is stwx a one-off?
Is this a question to whom? If to me I don't understand it.
stwx is part of a group of instructions. It's very rare that hardware only
shows certain behavior (like ignore a reserved bit) for single instructions.
Usually it happens on complete groups.
Who would know that? The test only tested stwx and I assume the same that
this should not behave differently than any other instruction. Also this
is the only instruction that was used with the set reserved bit in MorphOS
and the patch ignoring reserved bits for this group of instructions that
we discussed earlier seems to fix it. (There's another case with an
altivec instruction with a similar failure but I did not look at that yet
if that's a reserved bit too or something else.) As to why it's in MorphOS
I don't know, I got no answer from them.
Regards,
BALATON Zoltan
