Alex Williamson <alex.william...@redhat.com> : [...] > > Oh right, I looked for code references to the register but didn't notice > > that Linux configures it for MSI, not MSI-X. In my brief testing I only > > saw that Windows generates interrupts on the first vector, so perhaps > > not much lost without the extra vectors. I guess it's this patch that > > proves that MSI-X can be configured without this backdoor then. Do you > > have any insight into why this exists ?
No. I can only speculate that bar registers exhaustion and 64 bits decoders are not completely alien to this. Hayes may provide some hindsight. [...] > So the cycle is: > > word read from command register: I/O+ Mem+ BusMaster+ DisINTx+ SERR+ > > byte read from PCIe link control register[0]: CommClk+ > byte read from PCIe link control register[1]: nothing > > I'll be interested if that means anything to you. It's not a very high > rate access, the command register access is maybe 1Hz. Thanks, Nothing specific. It reminds me of rtl8168_esd_timer - kind of periodic sanity check - in Realtek's own 8168 driver but the pattern is a bit different. I need to check some recent revision of it though. -- Ueimor
