This behaviour can be changed after all needed Aarch64 (_EL3)
registers are implemented and respected at locations where
behaviour is different when EL3 is in Aarch64 state.
Signed-off-by: Fabian Aggeler <aggel...@ethz.ch>
---
target-arm/cpu.h | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 9e325ac..a4bb6bd 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -671,11 +671,15 @@ static inline bool arm_is_secure(CPUARMState *env)
/* Return true if the specified exception level is running in AArch64 state. */
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
{
- /* We don't currently support EL2 or EL3, and this isn't valid for EL0
+ /* We don't currently support EL2, and this isn't valid for EL0
* (if we're in EL0, is_a64() is what you want, and if we're not in EL0
* then the state of EL0 isn't well defined.)
*/
- assert(el == 1);
+ assert(el == 1 || el == 3);
+ /* EL3 can only run in Aarch32 at the moment */
+ if (el == 3) {
+ return false;
+ }
/* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
* is a QEMU-imposed simplification which we may wish to change later.
* If we in future support EL2 and/or EL3, then the state of lower
@@ -755,7 +759,6 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
} \
} while (0)
-
void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
/* Interface between CPU and Interrupt controller. */
--
1.8.3.2
