Add emulation of the PowerPC Decimal Floating Point Multiply instructions
dmul[q][.]
Signed-off-by: Tom Musta <tommu...@gmail.com>
---
target-ppc/dfp_helper.c | 22 ++++++++++++++++++++++
target-ppc/helper.h | 2 ++
target-ppc/translate.c | 4 ++++
3 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index 7fd7724..3a4e041 100644
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -261,6 +261,16 @@ static void dfp_check_for_VXISI_subtract(struct PPC_DFP
*dfp)
dfp_check_for_VXISI(dfp, 1);
}
+static void dfp_check_for_VXIMZ(struct PPC_DFP *dfp)
+{
+ if (dfp->context.status & DEC_Invalid_operation) {
+ if ((decNumberIsInfinite(&dfp->a) && decNumberIsZero(&dfp->b)) ||
+ (decNumberIsInfinite(&dfp->b) && decNumberIsZero(&dfp->a))) {
+ dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXIMZ, FP_VE);
+ }
+ }
+}
+
static void dfp_run_post_processors(struct PPC_DFP *dfp,
PPC_DFP_PostProc post_processors[], const size_t n)
@@ -311,3 +321,15 @@ PPC_DFP_PostProc SUB_PPs[] = {
DFP_HELPER_TAB(dsub, decNumberSubtract, SUB_PPs, 64)
DFP_HELPER_TAB(dsubq, decNumberSubtract, SUB_PPs, 128)
+
+PPC_DFP_PostProc MUL_PPs[] = {
+ dfp_set_FPRF_from_FRT,
+ dfp_check_for_OX,
+ dfp_check_for_UX,
+ dfp_check_for_XX,
+ dfp_check_for_VXSNAN,
+ dfp_check_for_VXIMZ,
+};
+
+DFP_HELPER_TAB(dmul, decNumberMultiply, MUL_PPs, 64)
+DFP_HELPER_TAB(dmulq, decNumberMultiply, MUL_PPs, 128)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 7ae8d03..17c75ab 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -622,4 +622,6 @@ DEF_HELPER_4(dadd, void, env, fprp, fprp, fprp)
DEF_HELPER_4(daddq, void, env, fprp, fprp, fprp)
DEF_HELPER_4(dsub, void, env, fprp, fprp, fprp)
DEF_HELPER_4(dsubq, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(dmul, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(dmulq, void, env, fprp, fprp, fprp)
#include "exec/def-helper.h"
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 80dc53c..a36ead4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -8360,6 +8360,8 @@ GEN_DFP_T_A_B_Rc(dadd)
GEN_DFP_T_A_B_Rc(daddq)
GEN_DFP_T_A_B_Rc(dsub)
GEN_DFP_T_A_B_Rc(dsubq)
+GEN_DFP_T_A_B_Rc(dmul)
+GEN_DFP_T_A_B_Rc(dmulq)
/*** SPE extension ***/
/* Register moves */
@@ -11291,6 +11293,8 @@ GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
+GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
+GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
#undef GEN_SPE
#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type,
PPC_NONE)
--
1.7.1
