Add a sysbus device consisting of a single ram. This allows for
instantiation of RAM just like any other device. There are a number
of good reasons to want to do this this:
1: Consistency. RAM is not that special where board level files should
have to instantiate it with a completely different API. This reduces
complexity of board level development by hiding the memory API
completely and handling everything via the sysbus API.
2: Device tree completeness. Ram Now shows up in info-qtree and
friends. E.g. Info qtree gives meaningful information under the
root system bus:
dev: sysbus-memory, id "zynq.ocm_ram"
size = 262144 (0x40000)
read-only = false
irq 0
mmio 00000000fffc0000/0000000000040000
dev: sysbus-memory, id "zynq.ext_ram"
size = 134217728 (0x8000000)
read-only = false
irq 0
mmio 0000000000000000/0000000008000000
3: Remove dependence of global state. Board files don't have to
explicity request the global singleton (and much unloved)
address_space_memory() and go hacking on it. address_space_memory()
is still ultimately used, but the ugliness is hidden in one place - the
sysbus core (we can fix that another day).
4: Data driven machine creation. There is list discussion on being able
to create or append-to sysbus machines in a data-driven way (whether
thats from command-line, monitor or scripts or whatever). This patch
removes the memory special case from that problem and allows RAM
instantiation to come via whatever solutions we come up with sysbus
device instantiation.
Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
---
hw/core/Makefile.objs | 1 +
hw/core/sysbus-memory.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 64 insertions(+)
create mode 100644 hw/core/sysbus-memory.c
diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs
index 5377d05..4a99840 100644
--- a/hw/core/Makefile.objs
+++ b/hw/core/Makefile.objs
@@ -9,6 +9,7 @@ common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o
common-obj-$(CONFIG_XILINX_AXI) += stream.o
common-obj-$(CONFIG_PTIMER) += ptimer.o
common-obj-$(CONFIG_SOFTMMU) += sysbus.o
+common-obj-$(CONFIG_SOFTMMU) += sysbus-memory.o
common-obj-$(CONFIG_SOFTMMU) += machine.o
common-obj-$(CONFIG_SOFTMMU) += null-machine.o
common-obj-$(CONFIG_SOFTMMU) += loader.o
diff --git a/hw/core/sysbus-memory.c b/hw/core/sysbus-memory.c
new file mode 100644
index 0000000..6361feb
--- /dev/null
+++ b/hw/core/sysbus-memory.c
@@ -0,0 +1,63 @@
+/*
+ * Sysbus Attached Memory.
+ *
+ * Copyright (c) 2014 Xilinx Inc.
+ * Written by Peter Crosthwaite <peter.crosthwa...@xilinx.com>
+ *
+ * This code is licensed under the GPL.
+ */
+
+#include "hw/sysbus.h"
+
+#define TYPE_SYS_BUS_MEMORY "sysbus-memory"
+
+#define SYS_BUS_MEMORY(obj) \
+ OBJECT_CHECK(SysBusMemory, (obj), TYPE_SYS_BUS_MEMORY)
+
+typedef struct SysBusMemory {
+ SysBusDevice parent_obj;
+
+ uint64_t size;
+ bool read_only;
+
+ MemoryRegion mem;
+} SysBusMemory;
+
+static void sysbus_memory_realize(DeviceState *dev, Error **errp)
+{
+ SysBusMemory *s = SYS_BUS_MEMORY(dev);
+
+ memory_region_init_ram(&s->mem, OBJECT(dev),
+ dev->id ? dev->id : "sysbus-memory", s->size);
+ memory_region_set_readonly(&s->mem, s->read_only);
+ vmstate_register_ram_global(&s->mem);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mem);
+}
+
+static Property sysbus_memory_props[] = {
+ DEFINE_PROP_UINT64("size", SysBusMemory, size, 0),
+ DEFINE_PROP_BOOL("read-only", SysBusMemory, read_only, false),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sysbus_memory_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->props = sysbus_memory_props;
+ dc->realize = sysbus_memory_realize;
+}
+
+static const TypeInfo sysbus_memory_info = {
+ .name = TYPE_SYS_BUS_MEMORY,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SysBusMemory),
+ .class_init = sysbus_memory_class_init,
+};
+
+static void sysbus_memory_register_types(void)
+{
+ type_register_static(&sysbus_memory_info);
+}
+
+type_init(sysbus_memory_register_types)
--
1.9.2.1.g06c4abd
