On 4/8/2014 2:58 PM, Alexander Graf wrote:
> On 04/08/2014 09:56 PM, Tom Musta wrote:
>> On 4/6/2014 3:55 PM, Alexander Graf wrote:
>> <snip>
>>
>>> @@ -806,6 +838,10 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env,
>>> uint32_t freq)
>>> tb_env = g_malloc0(sizeof(ppc_tb_t));
>>> env->tb_env = tb_env;
>>> tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
>>> + if (env->insns_flags & PPC_SEGMENT_64B) {
>>> + /* All Book3S 64bit CPUs implement level based DEC logic */
>>> + tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
>>> + }
>>> /* Create new timer */
>>> tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
>>> &cpu_ppc_decr_cb, cpu);
>>> if (0) {
>> Equating Book3S with PPC_SEGMENT_64B is clever ... is it too clever?
>> Especially since
>> the SLB Bridge is in the phased-out category and consequently we should
>> expect future
>> Book3S implementations to not support this instruction category.
>
> Maybe it's too clever :). I'm very open to suggestions on how to figure this
> out otherwise. Or maybe we should just rework the way timers get created and
> make them be part of the core itself?
>
I don't think there are existing flags that successfully describe what you want.
It seems to me that an overall timer configuration mechanism would be nice to
have. This would include:
- a list of timers supported by the processor (family)
- read / write privileges for each timer.
- additional attributes (e.g. edge triggered vs. level triggered DEC)
It would be great to have good default configurations for the current Book
III-S and Book III-E.
Things like read/write perms have changed over time which makes this all that
much more fun.
I need a little time to study Book III-E and review some old documents (e.g.
601, 401/403, etc.).
I'll propose something a little more concrete.
