On Mon, 2014-04-07 at 16:51 +0300, Marcel Apfelbaum wrote: > On Mon, 2014-04-07 at 16:34 +0300, Michael S. Tsirkin wrote: > > On Mon, Apr 07, 2014 at 02:44:06PM +0200, Gerd Hoffmann wrote: > > > Hi, > > > > > > > > + u8 shpc_cap = pci_find_capability(s->bus_dev, > > > > > PCI_CAP_ID_SHPC); > > > > > > > One thing I'd do is maybe check that the relevant memory type is > > > > enabled in the bridge (probably just by writing fff to base and reading > > > > it back). > > > > > > > This will give hypervisors an option to avoid wasting resources: > > > > e.g. it's uncommon for express devices to claim IO. > > > > > > I don't think we'll need that for the SHPC bridge. > > > > Why not? > Because "has shpc" => not an PCIe port. (as far as I know) > Anyway, why have shpc capability but no I/O or mem to support it? >
I signed too soon :), I have another question below, > Thanks, > Marcel > [...] > > > > So we should probe bridge for I/O support before wasting I/O resources on > > it. > > The spec does not provide a way to detect this, but we can do it like this: > > > > - write value ffffffff to I/O base register > Why write? A simple read would be enough. > It will never be 0(if I/O or mem is required) because of the "Base Address" > part of the register which represents the address range, right? Here ^^^ > > Thanks, > Marcel [...]
