This ensures the code generation debug code will honour -dfilter if set.
For the "exec" tracing I've added a new inline macro for efficiency's
sake. I've not touched CPU_LOG_TB_OP as this is buried in each
individual target.
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
----
v2 (wip)
- checkpatch updates
- add qemu_log_mask_and_addr macro for inline dump for traces
diff --git a/cpu-exec.c b/cpu-exec.c
index 40bdf88..abe02b7 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -49,8 +49,9 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu,
TranslationBlock *itb)
uintptr_t next_tb;
uint8_t *tb_ptr = itb->tc_ptr;
- qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n",
- itb->tc_ptr, itb->pc, lookup_symbol(itb->pc));
+ qemu_log_mask_and_addr(CPU_LOG_EXEC, itb->pc,
+ "Trace %p [" TARGET_FMT_lx "] %s\n",
+ itb->tc_ptr, itb->pc, lookup_symbol(itb->pc));
#if defined(DEBUG_DISAS)
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
diff --git a/include/qemu/log.h b/include/qemu/log.h
index 8cfe57f..f6cef9e 100644
--- a/include/qemu/log.h
+++ b/include/qemu/log.h
@@ -76,6 +76,21 @@ qemu_log_vprintf(const char *fmt, va_list va)
} \
} while (0)
+/* log only if a bit is set on the current loglevel mask
+ * and we are in the address range we care about:
+ * @mask: bit to check in the mask
+ * @addr: address to check in dfilter
+ * @fmt: printf-style format string
+ * @args: optional arguments for format string
+ */
+#define qemu_log_mask_and_addr(MASK, ADDR, FMT, ...) \
+ do { \
+ if (unlikely(qemu_loglevel_mask(MASK)) && \
+ qemu_log_in_addr_range(ADDR)) { \
+ qemu_log(FMT, ## __VA_ARGS__); \
+ } \
+ } while (0)
+
/* Special cases: */
/* cpu_dump_state() logging functions: */
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f1e0763..57d2b82 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2452,8 +2452,8 @@ static void dump_op_count(void)
#endif
-static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf,
- long search_pc)
+static inline int tcg_gen_code_common(TCGContext *s, uint64_t target_pc,
+ uint8_t *gen_code_buf, long search_pc)
{
TCGOpcode opc;
int op_index;
@@ -2461,7 +2461,8 @@ static inline int tcg_gen_code_common(TCGContext *s,
uint8_t *gen_code_buf,
const TCGArg *args;
#ifdef DEBUG_DISAS
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)
+ && qemu_log_in_addr_range(target_pc))) {
qemu_log("OP:\n");
tcg_dump_ops(s);
qemu_log("\n");
@@ -2489,7 +2490,8 @@ static inline int tcg_gen_code_common(TCGContext *s,
uint8_t *gen_code_buf,
#endif
#ifdef DEBUG_DISAS
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)
+ && qemu_log_in_addr_range(target_pc))) {
qemu_log("OP after optimization and liveness analysis:\n");
tcg_dump_ops(s);
qemu_log("\n");
@@ -2512,11 +2514,6 @@ static inline int tcg_gen_code_common(TCGContext *s,
uint8_t *gen_code_buf,
tcg_table_op_count[opc]++;
#endif
def = &tcg_op_defs[opc];
-#if 0
- printf("%s: %d %d %d\n", def->name,
- def->nb_oargs, def->nb_iargs, def->nb_cargs);
- // dump_regs(s);
-#endif
switch(opc) {
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
@@ -2581,7 +2578,7 @@ static inline int tcg_gen_code_common(TCGContext *s,
uint8_t *gen_code_buf,
return -1;
}
-int tcg_gen_code(TCGContext *s, uint8_t *gen_code_buf)
+int tcg_gen_code(TCGContext *s, uint64_t target_pc, uint8_t *gen_code_buf)
{
#ifdef CONFIG_PROFILER
{
@@ -2597,7 +2594,7 @@ int tcg_gen_code(TCGContext *s, uint8_t *gen_code_buf)
}
#endif
- tcg_gen_code_common(s, gen_code_buf, -1);
+ tcg_gen_code_common(s, target_pc, gen_code_buf, -1);
/* flush instruction cache */
flush_icache_range((uintptr_t)gen_code_buf, (uintptr_t)s->code_ptr);
@@ -2609,9 +2606,10 @@ int tcg_gen_code(TCGContext *s, uint8_t *gen_code_buf)
offset bytes from the start of the TB. The contents of gen_code_buf must
not be changed, though writing the same values is ok.
Return -1 if not found. */
-int tcg_gen_code_search_pc(TCGContext *s, uint8_t *gen_code_buf, long offset)
+int tcg_gen_code_search_pc(TCGContext *s, uint64_t tpc,
+ uint8_t *gen_code_buf, long offset)
{
- return tcg_gen_code_common(s, gen_code_buf, offset);
+ return tcg_gen_code_common(s, tpc, gen_code_buf, offset);
}
#ifdef CONFIG_PROFILER
diff --git a/tcg/tcg.h b/tcg/tcg.h
index f7efcb4..9200a25 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -559,8 +559,9 @@ void tcg_context_init(TCGContext *s);
void tcg_prologue_init(TCGContext *s);
void tcg_func_start(TCGContext *s);
-int tcg_gen_code(TCGContext *s, uint8_t *gen_code_buf);
-int tcg_gen_code_search_pc(TCGContext *s, uint8_t *gen_code_buf, long offset);
+int tcg_gen_code(TCGContext *s, uint64_t tpc, uint8_t *gen_code_buf);
+int tcg_gen_code_search_pc(TCGContext *s, uint64_t tpc,
+ uint8_t *gen_code_buf, long offset);
void tcg_set_frame(TCGContext *s, int reg, intptr_t start, intptr_t size);
diff --git a/translate-all.c b/translate-all.c
index f243c10..1bf8b5b 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -176,7 +176,7 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb,
int *gen_code_size_ptr
s->interm_time += profile_getclock() - ti;
s->code_time -= profile_getclock();
#endif
- gen_code_size = tcg_gen_code(s, gen_code_buf);
+ gen_code_size = tcg_gen_code(s, tb->pc, gen_code_buf);
*gen_code_size_ptr = gen_code_size;
#ifdef CONFIG_PROFILER
s->code_time += profile_getclock();
@@ -185,7 +185,8 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb,
int *gen_code_size_ptr
#endif
#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
+ if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)
+ && qemu_log_in_addr_range(tb->pc)) {
qemu_log("OUT: [size=%d]\n", *gen_code_size_ptr);
log_disas(tb->tc_ptr, *gen_code_size_ptr);
qemu_log("\n");
@@ -235,7 +236,8 @@ static int cpu_restore_state_from_tb(CPUState *cpu,
TranslationBlock *tb,
s->tb_jmp_offset = NULL;
s->tb_next = tb->tb_next;
#endif
- j = tcg_gen_code_search_pc(s, (uint8_t *)tc_ptr, searched_pc - tc_ptr);
+ j = tcg_gen_code_search_pc(s, tb->pc, (uint8_t *)tc_ptr,
+ searched_pc - tc_ptr);
if (j < 0)
return -1;
/* now find start of instruction before */
--
1.9.1
