On 03/19/2014 02:13 PM, Andreas Färber wrote: > Am 19.03.2014 22:04, schrieb Richard Henderson: >> Ping? This is a significant TCG code size regression >> for ARM, AArch64, and Sparc hosts. It helps x86 too, >> though that's not as severe. > > Sorry, applied to qom-cpu now: > https://github.com/afaerber/qemu-cpu/commits/qom-cpu > > How did you find this? Was there some assertion on one target, or do you > have some analysis code that you could share?
No assertions; all of the targets worked. I was just reading asm_out dumps as I improved the Sparc backend. We went from beginning with 0x40000000: ld [ %i0 + -76 ], %l0 to 0x40000000: sethi %hi(0xffffbc00), %g1 0x40000004: or %g1, 0x2ec, %g1 ! 0xffffbeec 0x40000008: ld [ %i0 + %g1 ], %l0 That constant is of course -16660, out of range of the 13-bit signed addend. Then I got to thinking: ARM also has a 13-bit range (though in a silly 1's compliment form), AArch64 has an 8-bit signed addend, and i386 can use a smaller encoding for an 8-bit signed addend. So it could benefit just about all of the backends to keep this offset relatively small. r~
