On Thu, Dec 17, 2009 at 6:27 PM, Richard Henderson <r...@twiddle.net> wrote:
> Defines setcond and movcond for implementing conditional moves at
> the tcg opcode level. 64-bit-on-32-bit is expanded via a setcond2
> primitive plus other operations.
>
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> tcg/README | 26 +++++++++++++++-
> tcg/tcg-op.h | 91
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> tcg/tcg-opc.h | 5 +++
> tcg/tcg.c | 23 ++++++++++----
> 4 files changed, 138 insertions(+), 7 deletions(-)
>
> diff --git a/tcg/README b/tcg/README
> index e672258..8617994 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -152,6 +152,11 @@ Conditional jump if t0 cond t1 is true. cond can be:
> TCG_COND_LEU /* unsigned */
> TCG_COND_GTU /* unsigned */
>
> +* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label
> +
> +Similar to brcond, except that the 64-bit values T0 and T1
> +are formed from two 32-bit arguments.
> +
> ********* Arithmetic
>
> * add_i32/i64 t0, t1, t2
> @@ -282,6 +287,25 @@ order bytes must be set to zero.
> Indicate that the value of t0 won't be used later. It is useful to
> force dead code elimination.
>
> +********* Conditional moves
> +
> +* setcond_i32/i64 cond, dest, t1, t2
> +
> +dest = (t1 cond t2)
> +
> +Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
> +
> +* movcond_i32/i64 cond, dest, c1, c2, vtrue, vfalse
> +
> +dest= (c1 cond c2 ? vtrue : of)
As malc already wrote this should be:
dest = (c1 cond c2 ? vtrue : vfalse)
> +
> +Set DEST to VTRUE if (c1 cond c2) is true, otherwise set to VFALSE.
> +
> +* setcond2_i32 cond, dest, t1_low, t1_high, t2_low, t2_high
> +
> +Similar to setcond, except that the 64-bit values T1 and T2 are
> +formed from two 32-bit arguments. The result is a 32-bit value.
> +
> ********* Type conversions
>
> * ext_i32_i64 t0, t1
> @@ -375,7 +399,7 @@ The target word size (TCG_TARGET_REG_BITS) is expected to
> be 32 bit or
>
> On a 32 bit target, all 64 bit operations are converted to 32 bits. A
> few specific operations must be implemented to allow it (see add2_i32,
> -sub2_i32, brcond2_i32).
> +sub2_i32, brcond2_i32, setcond2_i32).
>
> Floating point operations are not supported in this version. A
> previous incarnation of the code generator had full support of them,
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index faf2e8b..f43ed16 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -280,6 +280,32 @@ static inline void tcg_gen_op6_i64(int opc, TCGv_i64
> arg1, TCGv_i64 arg2,
> *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
> }
>
> +static inline void tcg_gen_op6i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
> + TCGv_i32 arg3, TCGv_i32 arg4,
> + TCGv_i32 arg5, TCGArg arg6)
> +{
> + *gen_opc_ptr++ = opc;
> + *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
> + *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
> + *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
> + *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
> + *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
> + *gen_opparam_ptr++ = arg6;
> +}
> +
> +static inline void tcg_gen_op6i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
> + TCGv_i64 arg3, TCGv_i64 arg4,
> + TCGv_i64 arg5, TCGArg arg6)
> +{
> + *gen_opc_ptr++ = opc;
> + *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
> + *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
> + *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
> + *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
> + *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
> + *gen_opparam_ptr++ = arg6;
> +}
> +
> static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
> TCGv_i32 arg3, TCGv_i32 arg4, TCGArg
> arg5,
> TCGArg arg6)
> @@ -1795,6 +1821,67 @@ static inline void tcg_gen_rotri_i64(TCGv_i64 ret,
> TCGv_i64 arg1, int64_t arg2)
> }
> }
>
> +static inline void tcg_gen_setcond_i32(int cond, TCGv_i32 ret,
> + TCGv_i32 arg1, TCGv_i32 arg2)
> +{
> + tcg_gen_op4i_i32(INDEX_op_setcond_i32, ret, arg1, arg2, cond);
> +}
> +
> +static inline void tcg_gen_setcond_i64(int cond, TCGv_i64 ret,
> + TCGv_i64 arg1, TCGv_i64 arg2)
> +{
> +#if TCG_TARGET_REG_BITS == 64
> + tcg_gen_op4i_i64(INDEX_op_setcond_i64, ret, arg1, arg2, cond);
> +#else
> + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
> + TCGV_LOW(arg1), TCGV_HIGH(arg1),
> + TCGV_LOW(arg2), TCGV_HIGH(arg2), cond);
> + tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
> +#endif
> +}
> +
> +static inline void tcg_gen_movcond_i32(int cond, TCGv_i32 ret,
> + TCGv_i32 cmp1, TCGv_i32 cmp2,
> + TCGv_i32 op_t, TCGv_i32 op_f)
> +{
> + if (TCGV_EQUAL_I32(op_t, op_f)) {
> + tcg_gen_mov_i32(ret, op_t);
> + return;
> + }
> + tcg_gen_op6i_i32(INDEX_op_movcond_i32, ret, cmp1, cmp2, op_t, op_f,
> cond);
> +}
> +
> +static inline void tcg_gen_movcond_i64(int cond, TCGv_i64 ret,
> + TCGv_i64 cmp1, TCGv_i64 cmp2,
> + TCGv_i64 op_t, TCGv_i64 op_f)
> +{
> + if (TCGV_EQUAL_I64(op_t, op_f)) {
> + tcg_gen_mov_i64(ret, op_t);
> + return;
> + }
> +#if TCG_TARGET_REG_BITS == 64
> + tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, cmp1, cmp2, op_t, op_f,
> cond);
> +#else
> + {
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + TCGv_i32 zero = tcg_const_i32(0);
> +
> + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0,
> + TCGV_LOW(cmp1), TCGV_HIGH(cmp1),
> + TCGV_LOW(cmp2), TCGV_HIGH(cmp2), cond);
> +
> + /* ??? We could perhaps conditionally define a movcond2_i32. */
> + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, zero,
> + TCGV_LOW(op_t), TCGV_LOW(op_f));
> + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, zero,
> + TCGV_HIGH(op_t), TCGV_HIGH(op_f));
> +
> + tcg_temp_free_i32(t0);
> + tcg_temp_free_i32(zero);
> + }
> +#endif
I agree movcond2 would be handy (though it can be argued
that anyway the speed of a 64-bit guest on a 32-bit host, where
it would matter the most, is low anyway).
I think it would also be nice to have to have a movtrue helper
that'd simply be movcond cond, dest, c1, c2, vtrue, dest.
All that can wait.
> +}
> +
> /***************************************/
> /* QEMU specific operations. Their type depend on the QEMU CPU
> type. */
> @@ -2067,6 +2154,8 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
> addr, int mem_index)
> #define tcg_gen_sari_tl tcg_gen_sari_i64
> #define tcg_gen_brcond_tl tcg_gen_brcond_i64
> #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
> +#define tcg_gen_setcond_tl tcg_gen_setcond_i64
> +#define tcg_gen_movcond_tl tcg_gen_movcond_i64
> #define tcg_gen_mul_tl tcg_gen_mul_i64
> #define tcg_gen_muli_tl tcg_gen_muli_i64
> #define tcg_gen_div_tl tcg_gen_div_i64
> @@ -2137,6 +2226,8 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv
> addr, int mem_index)
> #define tcg_gen_sari_tl tcg_gen_sari_i32
> #define tcg_gen_brcond_tl tcg_gen_brcond_i32
> #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
> +#define tcg_gen_setcond_tl tcg_gen_setcond_i32
> +#define tcg_gen_movcond_tl tcg_gen_movcond_i32
> #define tcg_gen_mul_tl tcg_gen_mul_i32
> #define tcg_gen_muli_tl tcg_gen_muli_i32
> #define tcg_gen_div_tl tcg_gen_div_i32
> diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
> index b7f3fd7..086968c 100644
> --- a/tcg/tcg-opc.h
> +++ b/tcg/tcg-opc.h
> @@ -42,6 +42,8 @@ DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
>
> DEF2(mov_i32, 1, 1, 0, 0)
> DEF2(movi_i32, 1, 0, 1, 0)
> +DEF2(setcond_i32, 1, 2, 1, 0)
> +DEF2(movcond_i32, 1, 4, 1, 0)
> /* load/store */
> DEF2(ld8u_i32, 1, 1, 1, 0)
> DEF2(ld8s_i32, 1, 1, 1, 0)
> @@ -82,6 +84,7 @@ DEF2(add2_i32, 2, 4, 0, 0)
> DEF2(sub2_i32, 2, 4, 0, 0)
> DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
> DEF2(mulu2_i32, 2, 2, 0, 0)
> +DEF2(setcond2_i32, 1, 4, 1, 0)
> #endif
> #ifdef TCG_TARGET_HAS_ext8s_i32
> DEF2(ext8s_i32, 1, 1, 0, 0)
> @@ -111,6 +114,8 @@ DEF2(neg_i32, 1, 1, 0, 0)
> #if TCG_TARGET_REG_BITS == 64
> DEF2(mov_i64, 1, 1, 0, 0)
> DEF2(movi_i64, 1, 0, 1, 0)
> +DEF2(setcond_i64, 1, 2, 1, 0)
> +DEF2(movcond_i64, 1, 4, 1, 0)
> /* load/store */
> DEF2(ld8u_i64, 1, 1, 1, 0)
> DEF2(ld8s_i64, 1, 1, 1, 0)
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index 3c0e296..f7ea727 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -670,6 +670,7 @@ void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
> }
> #endif
>
> +
Was this really needed? :-)
Laurent
> static void tcg_reg_alloc_start(TCGContext *s)
> {
> int i;
> @@ -888,21 +889,31 @@ void tcg_dump_ops(TCGContext *s, FILE *outfile)
> fprintf(outfile, "%s",
> tcg_get_arg_str_idx(s, buf, sizeof(buf), args[k++]));
> }
> - if (c == INDEX_op_brcond_i32
> + switch (c) {
> + case INDEX_op_brcond_i32:
> +#if TCG_TARGET_REG_BITS == 32
> + case INDEX_op_brcond2_i32:
> +#elif TCG_TARGET_REG_BITS == 64
> + case INDEX_op_brcond_i64:
> +#endif
> + case INDEX_op_setcond_i32:
> + case INDEX_op_movcond_i32:
> #if TCG_TARGET_REG_BITS == 32
> - || c == INDEX_op_brcond2_i32
> + case INDEX_op_setcond2_i32:
> #elif TCG_TARGET_REG_BITS == 64
> - || c == INDEX_op_brcond_i64
> + case INDEX_op_setcond_i64:
> + case INDEX_op_movcond_i64:
> #endif
> - ) {
> if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]])
> fprintf(outfile, ",%s", cond_name[args[k++]]);
> else
> fprintf(outfile, ",$0x%" TCG_PRIlx, args[k++]);
> i = 1;
> - }
> - else
> + break;
> + default:
> i = 0;
> + break;
> + }
> for(; i < nb_cargs; i++) {
> if (k != 0)
> fprintf(outfile, ",");
> --
> 1.6.5.2
>
>
