> Am 01.02.2014 um 15:35 schrieb BALATON Zoltan <bala...@eik.bme.hu>: > >> On Sat, 1 Feb 2014, Alexander Graf wrote: >> The assert happens inside the guest, so I'm afraid you'll have to add >> debugging output to edk2. Just print out the port number if port & 3 in the >> code path above. > > I've come this same conclusion too after I managed to enable qemu iport > debugging but it wasn't helpful. I've added logging to edk2 but I still don't > know what's going on. This is what I got: > > Without -M q35 where it works: > > (qemu) info pci > Bus 0, device 0, function 0: > Host bridge: PCI device 8086:1237 > id "" > Bus 0, device 1, function 0: > ISA bridge: PCI device 8086:7000 > id "" > Bus 0, device 1, function 1: > IDE controller: PCI device 8086:7010 > BAR4: I/O at 0xffffffffffffffff [0x000e]. > id "" > Bus 0, device 1, function 3: > Bridge: PCI device 8086:7113 > IRQ 0. > id "" > Bus 0, device 2, function 0: > VGA controller: PCI device 1013:00b8 > BAR0: 32 bit prefetchable memory at 0xffffffffffffffff [0x01fffffe]. > BAR1: 32 bit memory at 0xffffffffffffffff [0x00000ffe]. > BAR6: 32 bit memory at 0xffffffffffffffff [0x0000fffe]. > id "" > Bus 0, device 3, function 0: > Ethernet controller: PCI device 8086:100e > IRQ 0. > BAR0: 32 bit memory at 0xffffffffffffffff [0x0001fffe]. > BAR1: I/O at 0xffffffffffffffff [0x003e]. > BAR6: 32 bit memory at 0xffffffffffffffff [0x0003fffe]. > id "" > > PciBus: Resource Map for Root Bridge PciRoot(0x0) > Type = Io16; Base = 0xC000; Length = 0x1000; Alignment = 0xFFF > Base = 0xC000; Length = 0x40; Alignment = 0x3F; Owner = PCI > [00|03|00:14] > Base = 0xC040; Length = 0x10; Alignment = 0xF; Owner = PCI > [00|01|01:20] > Type = Mem32; Base = 0x80000000; Length = 0x2100000; Alignment = > 0x1FFFFFF > Base = 0x80000000; Length = 0x2000000; Alignment = 0x1FFFFFF; Owner > = PCI [00|02|00:10] > Base = 0x82000000; Length = 0x20000; Alignment = 0x1FFFF; Owner > = PCI [00|03|00:10] > Base = 0x82020000; Length = 0x1000; Alignment = 0xFFF; Owner > = PCI [00|02|00:14] > [...] > IoWrite32 CF8 80000820 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80000824 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80000828 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 8000082C > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80000830 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80000834 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80000838 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 8000083C > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80000804 > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80000804 > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80000B40 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 B008 > IoRead32 CF8 > IoWrite32 CF8 80000B40 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 B008 > > and so on repeating. With -M q35 where it stops at the assertion: > > (qemu) info pci > Bus 0, device 0, function 0: > Host bridge: PCI device 8086:29c0 > id "" > Bus 0, device 1, function 0: > VGA controller: PCI device 1013:00b8 > BAR0: 32 bit prefetchable memory at 0xffffffffffffffff [0x01fffffe]. > BAR1: 32 bit memory at 0xffffffffffffffff [0x00000ffe]. > BAR6: 32 bit memory at 0xffffffffffffffff [0x0000fffe]. > id "" > Bus 0, device 2, function 0: > Ethernet controller: PCI device 8086:100e > IRQ 0. > BAR0: 32 bit memory at 0xffffffffffffffff [0x0001fffe]. > BAR1: I/O at 0xffffffffffffffff [0x003e]. > BAR6: 32 bit memory at 0xffffffffffffffff [0x0003fffe]. > id "" > Bus 0, device 31, function 0: > ISA bridge: PCI device 8086:2918 > id "" > Bus 0, device 31, function 2: > SATA controller: PCI device 8086:2922 > IRQ 0. > BAR4: I/O at 0xffffffffffffffff [0x001e]. > BAR5: 32 bit memory at 0xffffffffffffffff [0x00000ffe]. > id "" > Bus 0, device 31, function 3: > SMBus: PCI device 8086:2930 > IRQ 0. > BAR4: I/O at 0xffffffffffffffff [0x003e]. > id "" > > PciBus: Resource Map for Root Bridge PciRoot(0x0) > Type = Io16; Base = 0xC000; Length = 0x1000; Alignment = 0xFFF > Base = 0xC000; Length = 0x40; Alignment = 0x3F; Owner = PCI > [00|1F|03:20] > Base = 0xC040; Length = 0x40; Alignment = 0x3F; Owner = PCI > [00|02|00:14] > Base = 0xC080; Length = 0x20; Alignment = 0x1F; Owner = PCI > [00|1F|02:20] > Type = Mem32; Base = 0x80000000; Length = 0x2100000; Alignment = > 0x1FFFFFF > Base = 0x80000000; Length = 0x2000000; Alignment = 0x1FFFFFF; Owner > = PCI [00|01|00:10] > Base = 0x82000000; Length = 0x20000; Alignment = 0x1FFFF; Owner > = PCI [00|02|00:10] > Base = 0x82020000; Length = 0x1000; Alignment = 0xFFF; Owner > = PCI [00|1F|02:24] > Base = 0x82021000; Length = 0x1000; Alignment = 0xFFF; Owner > = PCI [00|01|00:14] > [...] > IoWrite32 CF8 80001020 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80001024 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80001004 > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80001004 > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80001004 > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80001004 > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80001004 > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80001004 > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80001004 > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 8000100C > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 8000100C > IoWrite32 CF8 00000000 > IoRead32 CF8 > IoWrite32 CF8 80000B40 > IoRead32 CFC > IoWrite32 CF8 00000000 > IoRead32 6 > ASSERT .../edk2/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c(164): (Port & 3) > == 0 > > Does anybody have any hints on why this fails or how to debug it further?
Easiest is probably to attach gdb and get a backtrace to see who accesses that port. Alex > > Regards, > BALATON Zoltan
