For updating in kernel htab we need to provide both pte0 and pte1, hence update
the interface to take pte0 and pte1 together
Signed-off-by: Aneesh Kumar K.V <aneesh.ku...@linux.vnet.ibm.com>
---
hw/ppc/spapr_hcall.c | 20 ++++++--------------
target-ppc/mmu-hash64.c | 3 ++-
target-ppc/mmu-hash64.h | 22 ++++++++--------------
3 files changed, 16 insertions(+), 29 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 01cf6b05fee7..55d4eef1d960 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -51,7 +51,6 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment
*spapr,
target_ulong page_shift = 12;
target_ulong raddr;
target_ulong index;
- hwaddr hpte;
uint64_t token;
/* only handle 4k and 16M pages for now */
@@ -97,7 +96,6 @@ static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment
*spapr,
}
index = 0;
- hpte = pte_index * HASH_PTE_SIZE_64;
if (likely((flags & H_EXACT) == 0)) {
pte_index &= ~7ULL;
token = ppc_hash64_start_access(cpu, pte_index);
@@ -119,11 +117,9 @@ static target_ulong h_enter(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
}
ppc_hash64_stop_access(token);
}
- hpte += index * HASH_PTE_SIZE_64;
- ppc_hash64_store_hpte1(env, hpte, ptel);
- /* eieio(); FIXME: need some sort of barrier for smp? */
- ppc_hash64_store_hpte0(env, hpte, pteh | HPTE64_V_HPTE_DIRTY);
+ ppc_hash64_store_hpte(env, pte_index + index,
+ pteh | HPTE64_V_HPTE_DIRTY, ptel);
args[0] = pte_index + index;
return H_SUCCESS;
@@ -141,7 +137,6 @@ static RemoveResult remove_hpte(CPUPPCState *env,
target_ulong ptex,
target_ulong flags,
target_ulong *vp, target_ulong *rp)
{
- hwaddr hpte;
uint64_t token;
target_ulong v, r, rb;
@@ -161,8 +156,7 @@ static RemoveResult remove_hpte(CPUPPCState *env,
target_ulong ptex,
}
*vp = v;
*rp = r;
- hpte = ptex * HASH_PTE_SIZE_64;
- ppc_hash64_store_hpte0(env, hpte, HPTE64_V_HPTE_DIRTY);
+ ppc_hash64_store_hpte(env, ptex, HPTE64_V_HPTE_DIRTY, 0);
rb = compute_tlbie_rb(v, r, ptex);
ppc_tlb_invalidate_one(env, rb);
return REMOVE_SUCCESS;
@@ -269,7 +263,6 @@ static target_ulong h_protect(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
target_ulong flags = args[0];
target_ulong pte_index = args[1];
target_ulong avpn = args[2];
- hwaddr hpte;
uint64_t token;
target_ulong v, r, rb;
@@ -293,12 +286,11 @@ static target_ulong h_protect(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
r |= (flags << 48) & HPTE64_R_KEY_HI;
r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
rb = compute_tlbie_rb(v, r, pte_index);
- hpte = pte_index * HASH_PTE_SIZE_64;
- ppc_hash64_store_hpte0(env, hpte, (v & ~HPTE64_V_VALID) |
HPTE64_V_HPTE_DIRTY);
+ ppc_hash64_store_hpte(env, pte_index,
+ (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
ppc_tlb_invalidate_one(env, rb);
- ppc_hash64_store_hpte1(env, hpte, r);
/* Don't need a memory barrier, due to qemu's global lock */
- ppc_hash64_store_hpte0(env, hpte, v | HPTE64_V_HPTE_DIRTY);
+ ppc_hash64_store_hpte(env, pte_index, v | HPTE64_V_HPTE_DIRTY, r);
return H_SUCCESS;
}
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 11f3f6e731bb..fb297d62e3a6 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -558,7 +558,8 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env,
target_ulong eaddr,
}
if (new_pte1 != pte.pte1) {
- ppc_hash64_store_hpte1(env, pte_offset, new_pte1);
+ ppc_hash64_store_hpte(env, pte_offset / HASH_PTE_SIZE_64,
+ pte.pte0, new_pte1);
}
/* 7. Determine the real address from the PTE */
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index dc027f6d5264..3b6769ad130b 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -102,23 +102,17 @@ static inline target_ulong
ppc_hash64_load_hpte1(CPUPPCState *env,
}
}
-static inline void ppc_hash64_store_hpte0(CPUPPCState *env,
- hwaddr pte_offset, target_ulong pte0)
+static inline void ppc_hash64_store_hpte(CPUPPCState *env,
+ target_ulong pte_index,
+ target_ulong pte0, target_ulong pte1)
{
+ pte_index *= HASH_PTE_SIZE_64;
if (env->external_htab) {
- stq_p(env->external_htab + pte_offset, pte0);
+ stq_p(env->external_htab + pte_index, pte0);
+ stq_p(env->external_htab + pte_index + HASH_PTE_SIZE_64/2, pte1);
} else {
- stq_phys(env->htab_base + pte_offset, pte0);
- }
-}
-
-static inline void ppc_hash64_store_hpte1(CPUPPCState *env,
- hwaddr pte_offset, target_ulong pte1)
-{
- if (env->external_htab) {
- stq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2, pte1);
- } else {
- stq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1);
+ stq_phys(env->htab_base + pte_index, pte0);
+ stq_phys(env->htab_base + pte_index + HASH_PTE_SIZE_64/2, pte1);
}
}
--
1.8.5.3
