This patch series adds the branch and integer instructions that were introduced in Power ISA 2.07. Specifically,
- There is a new conditional Branch to Address Register (bctar) instruction. - The load/store quadword instructions are now supported in user mode (Book I). - Quadword atomic instructions have been added (lqarx, stqcx.). ISA 2.07 additions for other categories (VSX, Altivec, Decimal Floating Point, transactional memory) are not included in this patch series; they will be contributed via other patches. Tom Musta (8): target-ppc: Add Flag for bctar target-ppc: Add Target Address SPR (TAR) to Power8 target-ppc: Add bctar Instruction target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions target-ppc: Load Quadword target-ppc: Store Quadword target-ppc: Add Load Quadword and Reserve target-ppc: Add Store Quadword Conditional target-ppc/cpu.h | 9 ++- target-ppc/translate.c | 154 ++++++++++++++++++++++++++++++++++--------- target-ppc/translate_init.c | 19 +++++- 3 files changed, 146 insertions(+), 36 deletions(-)
