Populate the TxFIFO with the Tx data before sending. Prepares
support for proper Tx flow control implementation.
Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
---
hw/char/cadence_uart.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 3bcaf29..be32126 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -292,7 +292,22 @@ static void uart_write_tx_fifo(UartState *s, const uint8_t
*buf, int size)
return;
}
- qemu_chr_fe_write_all(s->chr, buf, size);
+ if (size > TX_FIFO_SIZE - s->tx_count) {
+ size = TX_FIFO_SIZE - s->tx_count;
+ /*
+ * This can only be a guest error via a bad tx fifo register push,
+ * as can_receive() should stop remote loop and echo modes ever getting
+ * us to here.
+ */
+ qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
+ s->r[R_CISR] |= UART_INTR_ROVR;
+ }
+
+ memcpy(s->tx_fifo + s->tx_count, buf, size);
+ s->tx_count += size;
+
+ qemu_chr_fe_write_all(s->chr, s->tx_fifo, s->tx_count);
+ s->tx_count = 0;
}
static void uart_receive(void *opaque, const uint8_t *buf, int size)
--
1.8.5.2
