On 11 December 2013 14:18, mihai.cara...@freescale.com <mihai.cara...@freescale.com> wrote: >> From: Peter Maydell [mailto:peter.mayd...@linaro.org] >> If the architecture spec says that a freshly reset physical CPU has >> coherent icache and dcache, then resetting the vCPU should also >> ensure the icache and dcache are coherent, so one way to solve >> this would be just to make sure that vcpu reset did the right thing. > > This is not related to reset operation. Freescale e500 core family > does not assure the coherency between data and instruction cache. > This is an extract from reference manual: > > 'When a processor modifies any memory location that can contain an > instruction, software must ensure that the instruction cache is made > consistent with data memory and that the modifications are made visible > to the instruction fetching mechanism. This must be done even if the > cache is disabled or if the page is marked caching-inhibited.' > > So it's the loader duty to synchronize the instruction cache.
But these are (emulated) ROMs, not an emulated bootloader. They ought to work like actual ROMs: QEMU as the emulator of the system/devices provides the contents of physical address space; KVM as the emulator of the CPU provides a CPU which doesn't start up executing from rubbish in its icache. (This matches how a real physical CPU executes its first instruction by really going out to the ROM, not by looking at its cache.) thanks -- PMM
