From: Antony Pavlov <antonynpav...@gmail.com>
Add an ARM CPU property for the reset value of hivecs as it is a
board/SoC configurable setting.
The existence of the property is conditional on the ARM CPU not being M
class.
Signed-off-by: Antony Pavlov <antonynpav...@gmail.com>
[ PC Changes:
* Elaborated commit message
* refactored to use object_property_add_bool_ptr
]
Signed-off-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index f32178a..afbd422 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -139,6 +139,7 @@ typedef struct ARMCPU {
uint32_t ccsidr[16];
uint32_t reset_cbar;
uint32_t reset_auxcr;
+ bool reset_hivecs;
} ARMCPU;
#define TYPE_AARCH64_CPU "aarch64-cpu"
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 44a6c28..f461abc 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -242,6 +242,12 @@ static void arm_cpu_post_init(Object *obj)
&err);
assert_no_error(err);
}
+
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
+ object_property_add_bool_ptr(obj, "reset-hivecs", &cpu->reset_hivecs,
+ &err);
+ assert_no_error(err);
+ }
}
static void arm_cpu_finalizefn(Object *obj)
@@ -303,6 +309,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
set_feature(env, ARM_FEATURE_PXN);
}
+ if (cpu->reset_hivecs) {
+ cpu->reset_sctlr |= (1 << 13);
+ }
+
register_cp_regs_for_features(cpu);
arm_cpu_register_gdb_regs_for_features(cpu);
--
1.8.5.1
