On 12/09/2013 10:12 AM, Peter Maydell wrote:
> From: Alex Bennée <alex.ben...@linaro.org>
>
> This adds support for the forms of ld/st with a 12 bit
> unsigned immediate offset.
>
> Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
> ---
> target-arm/translate-a64.c | 95
> +++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 94 insertions(+), 1 deletion(-)
>
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index 600cf63..ea3abc3 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -260,6 +260,17 @@ static TCGv_i64 read_cpu_reg(DisasContext *s, int reg,
> int sf)
> return v;
> }
>
> +static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
> +{
> + TCGv_i64 v = new_tmp_a64(s);
> + if (sf) {
> + tcg_gen_mov_i64(v, cpu_X[reg]);
> + } else {
> + tcg_gen_ext32u_i64(v, cpu_X[reg]);
> + }
> + return v;
> +}
Did you want to use this in for the load/store pair insns too?
r~
