On Tue, Nov 12, 2013 at 8:32 AM, Alex Williamson <alex.william...@redhat.com> wrote: > On Tue, 2013-11-12 at 07:55 +1000, Dave Airlie wrote: >> On Tue, Nov 12, 2013 at 7:43 AM, Alex Williamson >> <alex.william...@redhat.com> wrote: >> > When MSI is enabled on Nvidia GeForce cards the driver seems to >> > acknowledge the interrupt by writing a 0xff byte to the MSI capability >> > ID register using the PCI config space mirror at offset 0x88000 from >> > BAR0. Without this, the device will only fire a single interrupt. >> > VFIO handles the PCI capability ID/next registers as virtual w/o write >> > support, so any write through config space is currently dropped. Add >> > a check for this and allow the write through the BAR window. The >> > registers are read-only anyway. >> >> This is only half the truth, I'm afraid if I'm right its much worse than >> that. >> >> At least on some GPUs the MSI ack is done via PCI config space itself, >> and on some its done via the mirror, and yes it matters on some cards >> which way it works. > > I was hoping that wouldn't be the case since it seems fairly universal > that PCI config space access should be considered slow and avoided for > things like this. But, I suppose with MMConfig it's no worse than > device MMIO space.
For reference dig around in here http://www.mail-archive.com/nouveau@lists.freedesktop.org/msg14437.html nvidia commented on it as well, it may be they require the slowness or just some other coherency issue. Dave.
