On 7 November 2013 21:38, Marcel Apfelbaum <marce...@redhat.com> wrote: > Thanks Paolo, > Let me just point out what I know (or I think I know): > 1. Not all architectures have the behavior: "Address space that is not > RAM(and friends) is for sure PCI". > Only x86 behaves like this (I think).
More specifically, the x86 pc behaves like this. Other x86 based systems could in theory behave differently (not that we actually model any, I think). > That means that you cannot have a 64bit wide pci-hole > with lower priority that catches all accesses that are not for RAM(and > firends). ...but this conclusion is wrong, because the pci-hole region is created by the pc model. So we should create it at the correct priority and size to give the behaviour relative to other devices in the pc model that is required (ie that the hardware has). This doesn't affect any other target architecture or board. That said, I don't know enough about the PC to know what the exact details of the pci-hole are, so I'm not making a statement about what the correct model is. I'm just saying that what you do with the pci-hole and the container it lives in and the other devices in that container is not going to change the behaviour of any other target board. > 2. If the above is right, and making pci-hole 64 bit wide is not an option, > playing with pci-holes/other-region priorities it would be just wrong, > it would be only to "fight" with the locality of the memory region's > priority. I have no idea what you mean by "fighting" here. MR priorities apply only within a specific container region[*], to set which of that container's children appears 'above' another. They're totally local to the container (which in this case is part of the PC model, not the generic PCI code) and so the PC model can freely set them to whatever makes most sense. [*] if you didn't already know this, see the recently committed updates to doc/memory.txt for a more detailed explanation. -- PMM
