Il 06/10/2013 22:34, Paolo Bonzini ha scritto: > Il 06/10/2013 20:28, Michael S. Tsirkin ha scritto: >>>>> For each PCI device I tried creating a VM with an instance of it (a few >>>>> devices at a time), and did VM resets. Earlier versions were tested by >>>>> the guy who reported the SCSI problems. >>>> >>>> x86 kvm only? >>> >>> Yes. >> >> Hmm, I'm not sure that's enough for this kind of change. > > I'll do more tests though, from looking at the source code, I'm not sure > what could happen depending on the host bridge.
Did more tests, PPC g3beige and PPC64 mac99 both work. I also tested resetting the secondary bus of a PCI bridge (via setpci), and it also works as expected. Finally, I looked more at the history of the code to justify patch 2. Initially, zeroing the irq_state was added in commit 6eaa684 (Add pci_bus_reset() function., 2009-06-17) to deal with this issue: >> Shouldn't each device's reset function bring its line low, thus zeroing >> the irq_state naturally? >> >> If not, we have a bug somewhere. Note we have exactly the same issue >> with save/restore. >> > They should, but I haven't found one that does. More registers were then cleared by pci_device_reset in your commit c0b1905 (qemu/pci: reset device registers on bus reset, 2009-09-16). Deasserting interrupts explicitly came in later as part of PCI bus and FLR support in commit 4c92325 (pci: deassert intx on reset., 2011-01-20). That should be the point where the code starts following the invariant of patch 2. Paolo
