From: Alexander Graf <ag...@suse.de>
The cpu_env tcg variable will be used by both the AArch32 and AArch64
handling code. Unstaticify it, so that both sides can make use of it.
Signed-off-by: Alexander Graf <ag...@suse.de>
Signed-off-by: John Rigby <john.ri...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Message-id: 1378235544-22290-5-git-send-email-peter.mayd...@linaro.org
Message-id: 1368505980-17151-3-git-send-email-john.ri...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target-arm/translate.c | 2 +-
target-arm/translate.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 450a0b6..2605833 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -61,7 +61,7 @@ static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
#define DISAS_WFI 4
#define DISAS_SWI 5
-static TCGv_ptr cpu_env;
+TCGv_ptr cpu_env;
/* We reuse the same 64-bit temporaries for efficiency. */
static TCGv_i64 cpu_V0, cpu_V1, cpu_M0;
static TCGv_i32 cpu_R[16];
diff --git a/target-arm/translate.h b/target-arm/translate.h
index e727bc6..8ba1433 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -24,4 +24,6 @@ typedef struct DisasContext {
int vec_stride;
} DisasContext;
+extern TCGv_ptr cpu_env;
+
#endif /* TARGET_ARM_TRANSLATE_H */
--
1.7.9.5
