Hello Eduardo, I read a bit about caches on wikipedia.
If I understand correctly changing the CPUID L3 cache infos in QEMU will change the value displayed in the guest /proc/cpuinfo but will not change the size of the l3 cache used by the hardware. So I am chasing a cosmetic bug. If it right ? > > Do you have some recommandations regarding the other fields of the edx > > register ? > > Probably it will be a good idea to let each CPU model have their own > defaults for the cache information. Do you mean querying the host CPUID registers and forwarding the values to the guest ? > > > What would be an acceptable user interface to set this ? > > Things I can remember from the top of my head: > > * It would be interesting to redo this patch, before doing anything else: > > https://github.com/ehabkost/qemu-hacks/commit/10b675fa1269a65a553586545fdbcd95ace79d65 > * We need to keep compatibility on existing machine-types (not change > the cache size); > * If some information is reported on multiple CPUID leaves, we need to > keep them consistent with each other (see the FIXME comments on the > URL above); I could write a patch to fix broken CPUID leaves. But how would it work regarding compatibility ? Is it right to just fix the leaves or does the machine type rule apply here ? Best regards Benoît
