On Fri, 2013-07-12 at 05:18 +0200, Alexander Graf wrote: > We model a single system wide io space today and access to that one > happens through you pci host controller. I just messed up the > terminology here.
Single system wide IO space is broken. We have separate IO space per PHB. That was working afaik. In any case, I completely object to all that business with conversion in bridges. That's fundamentally WRONG. The whole business of endianness in qemu is a mess. In the end what matters and the only thing that does is: * The endianness of a given memory access by the guest (which may or may not be the endianness of the guest -> MSR:LE, byteswap load/store instsructions, etc..) vs. * The endianness of the target device register (and I say register ... a framebuffer does NOT have endianness per-se and thus accesses to BAR mapping a "memory" range (framebuffer, ROM, ...) should go such that the *byte order* of individual bytes is preserved, which typically means untranslated). Unless they are completely broken (and those exist, don't get me wrong, though mostly they are a thing of a past long gone), bridges and busses have no effect on endianness. So I'm not sure what you guys are up to, but from what I read, it's wrong, and the fact at this stage is that your broke IO space (and thus virtio and VGA) on powerpc (including pseries). Cheers, Ben.
